Design Overview for s3_vsmpl

PropertyValue
Project Name:f:\yacc\syn\xilinx
Target Device:xc3s200
Report Generated:Saturday 08/27/05 at 10:20
Printable Summary (View as HTML)s3_vsmpl_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:1,1473,84029% 
Number of 4 input LUTs:3,2023,84083% 
Logic Distribution:    
Number of occupied Slices:1,9181,92099% 
Number of Slices containing only related logic:1,8971,91898% 
Number of Slices containing unrelated logic:211,9181% 
Total Number 4 input LUTs:3,3043,84086% 
Number used as logic:3,202   
Number used as a route-thru:101   
Number used as Shift registers:1   
Number of bonded IOBs:10317359% 
Number of Block RAMs:111291% 
Number of MULT18X18s:21216% 
Number of GCLKs:2825% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentSaturday 08/27/05 at 09:55
Translation ReportCurrentSaturday 08/27/05 at 10:04
Map ReportCurrentSaturday 08/27/05 at 10:05
Pad ReportCurrentSaturday 08/27/05 at 10:08
Place and Route ReportCurrentSaturday 08/27/05 at 10:08
Post Place and Route Static Timing ReportCurrentSaturday 08/27/05 at 10:08
Bitgen ReportCurrentSaturday 08/27/05 at 10:20