Design Overview for yacc

PropertyValue
Project Name:f:\yacc\syn\xilinx
Target Device:xc3s200
Report Generated:Thursday 04/14/05 at 21:07
Printable Summary (View as HTML)yacc_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:1,1483,84029% 
Number of 4 input LUTs:3,1983,84083% 
Logic Distribution:    
Number of occupied Slices:1,9181,92099% 
Number of Slices containing only related logic:1,8991,91899% 
Number of Slices containing unrelated logic:191,9181% 
Total Number 4 input LUTs:3,2993,84085% 
Number used as logic:3,198   
Number used as a route-thru:101   
Number of bonded IOBs:5317330% 
Number of Block RAMs:111291% 
Number of MULT18X18s:21216% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Number of Unrouted Signals:All signals are completely routed.
Number of Failing Constraints:0

Failing Constraints

Constraint(s)RequestedActualLogic Levels
No Constraints Found   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentThursday 04/14/05 at 21:03
Translation ReportCurrentThursday 04/14/05 at 21:04
Map ReportCurrentThursday 04/14/05 at 21:04
Pad ReportCurrentThursday 04/14/05 at 21:07
Place and Route ReportCurrentThursday 04/14/05 at 21:07
Post Place and Route Static Timing ReportCurrentThursday 04/14/05 at 21:07