Design Overview for ram_module_altera

PropertyValue
Project Name:f:\yacc\syn\xilinx
Target Device:xc3s200
Report Generated:Sunday 04/10/05 at 15:43
Printable Summary (View as HTML)ram_module_altera_summary.html

Device Utilization Summary

Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops:23,8401% 
Number of 4 input LUTs:1783,8404% 
Logic Distribution:    
Number of occupied Slices:921,9204% 
Number of Slices containing only related logic:9292100% 
Number of Slices containing unrelated logic:0920% 
Total Number of 4 input LUTs:1783,8404% 
Number of bonded IOBs:13617378% 
Number of Block RAMs:81266% 
Number of GCLKs:1812% 

Performance Summary

PropertyValue
Data Not Yet Available  

Failing Constraints

Constraint(s)RequestedActualLogic Levels
Data Not Yet Available   

Detailed Reports

Report NameStatusLast Date Modified
Synthesis ReportCurrentSunday 04/10/05 at 15:43
Translation ReportCurrentSunday 04/10/05 at 15:43
Map ReportCurrentSunday 04/10/05 at 15:43