Property | Value |
Project Name: | f:\yacc\syn\xilinx |
Target Device: | xc3s200 |
Report Generated: | Saturday 08/27/05 at 10:20 |
Printable Summary (View as HTML) | s3_vsmpl_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops: | 1,147 | 3,840 | 29% | |
Number of 4 input LUTs: | 3,202 | 3,840 | 83% | |
Logic Distribution: | ||||
Number of occupied Slices: | 1,918 | 1,920 | 99% | |
Number of Slices containing only related logic: | 1,897 | 1,918 | 98% | |
Number of Slices containing unrelated logic: | 21 | 1,918 | 1% | |
Total Number 4 input LUTs: | 3,304 | 3,840 | 86% | |
Number used as logic: | 3,202 | |||
Number used as a route-thru: | 101 | |||
Number used as Shift registers: | 1 | |||
Number of bonded IOBs: | 103 | 173 | 59% | |
Number of Block RAMs: | 11 | 12 | 91% | |
Number of MULT18X18s: | 2 | 12 | 16% | |
Number of GCLKs: | 2 | 8 | 25% |
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Saturday 08/27/05 at 09:55 |
Translation Report | Current | Saturday 08/27/05 at 10:04 |
Map Report | Current | Saturday 08/27/05 at 10:05 |
Pad Report | Current | Saturday 08/27/05 at 10:08 |
Place and Route Report | Current | Saturday 08/27/05 at 10:08 |
Post Place and Route Static Timing Report | Current | Saturday 08/27/05 at 10:08 |
Bitgen Report | Current | Saturday 08/27/05 at 10:20 |