5.1.4 Memory with initialized value
Af first,make memory initialization file by Using Quartas2.
This is an example.
Memory words = 1024 ,and bit width of word =32bits
Memory pattern is incremental here in example.
Save Mif file as Hex. (Since Veritak can not read mif file directly, we use HEX file, which
should be converted to verilog file by altera_mf.v.)
Set appropriate bit width and words in MegaWizard.
Set HEX file(generated by above operation) as memory initialization file.
Simulation by RTL (altera\sram_initialize_HEX)
Simulation by Gate (altera\sram_initialize_HEX\simulation\custom)
Set "NO_PLI" in a project as follows. Th sample project is located in altera\sram_initialize_MIF folder.
5.1.5MegaWizard Generated IP's simulation
You can simulate WegaWizard generated gate-level simulation model. The generated extension is .vo.
( The gate level models are generated by checking "Generate Simulation
Model " in MegaWizard as well as simple test bench.)
The following is an example of project by using SratixV for DDR3 controller.