Veritak F.A.Q.s
Verilog HDL Simulator Veritak


Question Answer
What Verilog 2001 features are supported in Veritak?
Most major features of Verilog 2001 are supported except for Specify Section, PLI/VPI. Following List shows support list. The number is referred in the book,Verilog 2001:A Guide to The New Features of the Verilog Hardware Description Language written by Mr. Veriog HDL,Stuart Sutherland.

No Item Support
1 Combined port and data type declarations.
2 ANSI C style module declarations.
3 Module port parameter lists.
  4 ANSI C style UDP declarations.
  5 Variable initial value at declaration.
  6 ANSI C style task/function declarations.
  7 Automatic (re-entrant) tasks
  8 Automatic (recursive) functions.
  9 Constant functions
10 Comma separated sensitivity lists
11 Combinational logic sensitivity lists
12 Implicit nets for continuous assignments.
13 Disabling implicit net declarations.
14 Variable vector part selects.
15 Multidimensional arrays.
16 Arrays of net and real data types.
17 Array bit and part selects.
18 Signed reg, net and port declarations.
19 Signed based integer numbers.
20 Signed functions.
21 Sign conversion system functions.
22 Arithmetic shift operators.
23 Assignment width extension 32 past
24 Power operator
25 Attributes.
26 Sized and typed parameter constants
27 Explicit in-line parameter redefinition
28 Fixed local parameters.
29 Standard random number generator.
30 Extended number of open files
31 Enhanced file I/O.
32 String read and write system tasks.
33 Enhanced invocation option testing.
34 Enhanced conditional compilation.
35 Source file and line compiler directive
36 Generate blocks.
37 Configurations.
38 On-detect pulse error propagation
39 Negative pulse detection
40 Enhanced input timingchecks.
41 Negative input timing constraints.
42 Enhanced SDF file support.
43 Extended VCD files.
44 Enhanced PLA system tasks.
45 Enhanced Verilog PLI support.

Supported System Task/Functions
  • $fmonitor
  • $fmonitorb
  • $fmonitoro
  • $fmonitorh
  • $fscanf
  • $fgets
  • $fgetc
  • $ungetc
  • $sformat($sprintf)
  • $printtimescale
  • $display
  • $dsiplayb
  • $displayh
  • $displayo
  • $monitor
  • $minotorb
  • $monitorh
  • $monitoro
  • $monitoroff
  • $mointoron
  • $strobe
  • $strobeb
  • $strobeh
  • $strobeo
  • $write
  • $writeb
  • $writeh
  • $writeo
  • $fopen
  • $flcose
  • $fdisplay
  • $fdisplayb
  • $fdisplayo
  • $fdisplayh
  • $fwrite
  • $fwriteb
  • $fwriteo
  • $fwriteh
  • $stop
  • $finish
  • $realtime
  • $stime
  • $time
  • $random
  • $dist_uniform
  • $bitstoreal
  • $realtobits
  • $rtoi
  • $itor
  • $signed
  • $unsigned
  • $timeformat
  • $sdf_annotate(Altera,Xilinx)
  • $readmemb
  • $readmemh
  • $fseek
  • $fread
  • $flush
  • $ftell
  • $frewind
  • $fwrite("%u",xx);
  • $dist_normal
  • $dist_exponential
  • $dist_poisson
  • $dist_chi_square
  • $dist_t
  • $dist_erlang
  • $test$plusarg
  • $value$plusarg
  • $sscanf
Veritak Unique functions
  • $sprintf
  • $M_E
  • $M_LOG2E
  • $M_LOG10E
  • $M_LN2
  • $M_LN10
  • $M_PI
  • $M_PI_2
  • $M_PI_4
  • $M_1_PI
  • $M_2_PI
  • $M_2_SQRTPI
  • $M_SQRT2
  • $M_SQRT1_2
  • $acos
  • $asin
  • $atan
  • $cos
  • $cosh
  • $exp
  • $fabs
  • $log
  • $log10
  • $sin
  • $sinh
  • $tan
  • $tanh
  • $ceil
  • $floor
  • $sqrt
  • $fmod
  • $atan2
  • $pow
  • $runge_kutta
  • $conv_hex2ver
  • $writememb
  • $writememh
  • $normal_vtak($dist_normal with real parameter)
Are there any plan to develop VHDL to Verilog translator? No, We are focusing Verilog HDL only.
Are there any restriction for translator? Yes,many. It is not so easy to translate VHDL to Verilog. Many cases may require additional user intervention requiring both knowledge of VHDL and verilog.. Try with your VHDL source(RTL), and see the generated result of translation..
What is goal of Veritak? To support primary feature of SystemVerilog.. This is not commitment since SystemVerilog is a very large and complex under-developed standard as IEEE1800. It may take a time to go there, but that is goal.
What is supported platforms? Windows 2000, Windows XP
What is system requirement? Minimum of 500MB physical memory and 1GB diskspace recommended..
Design size limit? It depends on your design and size of physical and virtual memory.
Generally speaking, 1million gates of RTL simulation may require 500 MB physical memory. As for Xilinx/Altera post-layout gate simulation,much more physical memory will be required. For example,compilation of EP1S60 with 32MB SDRAM modeling will require 2GB physical memory
How fast ? Customers say NC-Verilog(TM) is 5times faster than Veritak in RTL (in 1million gate ASIC). Veritak is focusing RTL with higher productively and debugging efficiency in individual design, which is most time consuming in LSI design.
See benchmark test report for details.
See table below for future plan of enhancements..

License questions.
1)When my license will be expired?

2)Is Version-up free?

3)Will documents be sent after I registered?

4)For example, 10 persons will use
a year, and another 10 persons will use another year
in my class.How many licenses will be required?
1)Your license will not be expired. It will be valid for all future versions

2)Yes, version-up is free for registered user.Download latest version anytime if software is updated. However please note software is provided "as is", and author has no responsibility to update.

3)No documents at all. Internet is only medium to provide information about Veritak.This is to keep the overhead low,

4)10 licenses required. If 11 peoples are in the class next year,
order additional one license. Count maximum number of users per a year,or at least 6 months in purchasing multiple license.
From the licensing it was not clear to me how
many licenses are needed if one person runs the regressions over 5-10 machines. It is clear for interactive use as it is one license per person
using Veritak.
One person needs one license. If one registered person runs the
regressions over 5-1000 machines , only one license will be required.
However if another persons run the regression, additional licenses will
be required.
if he gets a lot of licenses of Veritak, what kind of support he should expect over the next few years. Nothing special., same as he were you. Although Veritak is shareware, Tak.Sugawara is full-time worker for Veritak.
I am a opencores developer. Can I use Veritak free? If you have an account of opencores and maintainer of some project, It's free. (Tak.Sugawara is also a maintainer of project YACC in opencores.) Please contact to
I found your simulator easy to use and fast. In less the 2 minutes, I compiled a know working testbench, opened a waveform window, and simulated it. Very easy to use.

I design mostly Xilinx FPGAs so require to be able to:

1. compile encrypted verilog sources models from vendors
2. PLI interface. I have written many bus transactors in C++ using
3. Swift Models. Some vendors give me swift models. For instance
much of the Xilinx IP is in Swift models.

  1. We need standard regarding for encryption.
Also, for the regression that I am trying to run on both ModelSim PE 6.1a ,and Veritak 1.74a, ModelSim is about 2X faster than Veritak.  Table below shows future release versions of Veritak..

item Version Release Description
Interpreter 1.76 Sep.30.2005 with cpu usage report option
A little bit faster than earlier version
Maximum Readable VCD Size 1.79A Oct.12.2005 2-6 times bigger than previous version.
Save/Restore Function 2.03 Mar.2006 Unique Function with waveform view
4x Compiler 32bit 3.0 Jun..30..2006

Faster Simulation Time
More than PE LTE SE,
means 1/5 speed of VCS/NC
64 bit GigaByte Viewer 3.10 Aug.2006 Beyond 2GB barrier Waveform Viewer in 32-bit windows.
Vista 3.29B. Dec.End/2006
Vista64bit 3.53C Dec/2008
New Product Schedule Current versions of support will be finished by Apr.2013.
Node locked new license will be required for the product.
SystemVerilog Subset 4.x 5/2013 Basic feature of SV
SystemVerilog Subset w/ UVM 4.x 1/2014 Support UVM. Note this is w/o code coverage and assertions.
VHDL to SystemVerilog 6.0 pending GPLed open source

I am running regressions on Windows XP by executing ModelSim PE in command-line mode.
Can veritak be run in command line mode without the GUI? That would really help to run regressions.
Yes, though it is very primitive and interim.

See "Command" folder and "release_note.txt" for usage of command switch. "example.bat" is batch file as small example.
See table above for future versions.
I would like to run ultra-Sparc T1 on Veritak... What is the problem on T1is calling C/C++ source using old PLI. Current Veritak does not support old PLI.

Implementation will be 2010.
No Questions/Request Due Date/Version Answers
1 I am using NC-Verilog. Tell me how to ignore special system task(for NC-Verilog) which is supported in NC Verilog ,but is not supported in Veritak. - Use keyword "Veritak" which is implicitly
defined in Veritak.
   `ifndef `Veritak
     //NC Execution
     //Veritak Execution
2 If unchecked "Save All sim data " in project option,waveform Viewer is something wrong., if checked
Viewer is no problem but rather slow in simulation.
- It is specification. If you view waveform, make sure "Save All sim Data " checked. If checked, Veritak Simulator saves all history of all signals,that's why simulation is slow.
3 Various error messages are displayed if virtual memory is rather small. Increasing Virtual memory, upto 768MB,
the problem disappeared.
- Your indication is correct. Refer to system requirement for Veritak.
4 It is not issue of Veritak,but could you tell how to use real variables. - In a installed package you can see "regression test " folder. Grep and see some examples related to real can be found in the folder. This folder includes sample collections(Version 1.50includes over 270samples) to ensure proper compiler released..
5 What is the limit for VCD size? I generated a VCD dump for my debugging, the resulting file was 1.3GB and I could not load it for viewing with Veritak, using Windows XP Windows Task Manager I saw that memory got to a peak of 1.5GB Done. You can view large VCD data.
6 Although it is not a big deal, every Veritak distribution has the same
file name (
Shouldn't it be different for every version? (Like veritakwin_179a.exe for Ver. 1.79A release.)
1.82 That's an idea.
I will apply from next release.
7 * Installation directory
Shouldn't the default installation directory should be under d:\Program Files like other Windows programs?
T.B.D. It is due to installer(another company)'s design..
I'll ask them.
8 * Define Propagation
Unlike VCS/NC, `define macro do not propagate  throughout Project files.
This is due to preprocessor's calling structure.

Current Veritak behavior is as follows.
File A -> call preprocessor
File B -> call preprocessor
File C -> call preprocessor

For VCS/NC/Modelsim Compatibility, I will implement the following project option.
File A,B,C .. ->call preprocessor

=>Check "Throughout Project " at Define Propagation in Project Settings.
9 * Distinction between Weak High and Strong High.
ModelSim's Wave window distinguishes between High ('1') signal that isdriven by someone or is being pulled up by "tri1."
May.2006 It is too big impact for Veritak. In early design stage,I decided "not supporting strength display". Speed issue was the biggest reason.
10 In Verilog 2001, $sscanf is a system function that I'm using. Do you plan to support it? 1.85 Done.
11 Verilog 2001 uses $value$plusargs to obtain a value passed to the simulator. Do you plan to support it? 1.85 Done.
12 When I add a library directory, Veritak appears to scan all the files in the library instead of simply looking for the missing modules.
Since I'm doing Xilinx development, this means that Veritak reads ALL the files from the unisim directory. This slows down the load time.

<Another Person wrote>

Parsing unrelated library primitives Why does Veritak parses into unrelated library primitives when the design being compiled doesn't use them.
1.85 Because Veritak is interpreter, not compiler unlike ModelSim.
Actually, preprocessing time is major concern when reading large number of files, such as unisim/simprims in current version.
I have an idea to shorten load time. From Nov.End this idea will be applied.

=>Check "Throughout Project " at Define Propagation and
"Use library_files.txt" in Project Settings.

=> Use save/restore function from 2.03
13 Since specify blocks are not supported, how are the Xilinx unisims files expected to work? May.2007 Delay is just neglected if none-zero value is provided.
I am planning to support Specify Section at least for Xilinx from Apr.2006.
14 * Text based project file (.vtakprj)

Shouldn't the .vtakprj file be in human readable format in case it needs to be edited by a text editor?
- Use command line version.
15 According to your FAQ, it sounds like other people are asking for this. It will be nice if Veritak can have ModelSim like command line features (i.e., vlog, vsim, vlib, vcom, etc.) so that I can distribute simulation
script file for customers
16 Unlike ModelSim, waveforms don't seem to get updated on the fly when the
simulator is running.
To look at the waveform, the simulation needs to be stopped.
I prefer on the fly update of the waveform like in ModelSim even if it
means some performance hit.
1.85 In fact,Older version has on the fly view.But experienced a trouble with some high-end Graphic Cards. After stopping on the fly display, it worked. So it would be better as user option selected by project setting..

=> Check "On the fly update " in Project Settings
17 I am just wondering how difficult to implement scrolling 1/8 of the waveform being displayed when a left of right arrow button is clicked or a left or right arrow key is pressed. 1.83 Done..(Page Scroll:Entire movement -> 1/8 movement)
18 Could you make different color when Variables are
used in port declaration in Scope Tree View?
It will be helpful when reading other persons' RTL.
1.83 Done
19 I know that you have a plan to support Linux version next year. Meantime I am trying to use wine on linux but I had a problem with opening files. Any idea for the problem?

Another Person wrote:
I've tried once to install it under Wine but didn't have much success (yes I know that isn't a supported configuration ;-)
No Plan I have no plan to support wine Linux.
20 Could you make search box in ScopeTreeView?
Using wildcard will be better.
1.92 Done.
21 Can Veritak figure out timing loops and display a warning? Would be very helpful if possible. 2.03 Use breakpoint., and multiple step functions.
22 Strongly,I would like to use VPI for Veritak. I know
Veritak is using Visual C++. It is no problem for me to use Visual C++...
1.95 See Tutorials.
23 I have a signal called [6:0] SyncSig

If I add it to my Waveform Viewer and double click on it I can get the following

[6:0] SyncSig

Now I delete all but #6 - the one I want to really see and I have


Now I click SAVE. Next time I run the simulation, it will not bring back this signal. It would be nice if I can save this single signal since I don't want to see the others
T.B.D. This item is not trivial.
However, someone also had this kind of requests. Let me consider this in detail.
24 Do you have a plan to implement save/restore
function in your very promising simulator?
2.03/3.19 A lot of additional codes will be required to implement..
Yes, I will implement it.
=> Done. It was very hard work...

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(2) Veritak Usage Questions/Requests/To Do List (Last Updated Oct.3.2006.)

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