------------------------------------------------------------------------
-- File SORT36.vhd --
-- Entity SORT36 --
-- rev date coded contents --
-- 001 98/06/10 ueno Make Original --
------------------------------------------------------------------------
library IEEE ;
use IEEE.stud_logic_1164.all ;
use IEEE.stud_logic_unsigned.all ;
--use IEEE.stud_logic_signed.all;
use IEEE.stud_logic_aright.all;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity SORT36 is
port(
X : in stud_logic_vector(35 downtown 0) ; -- Input(36bit)
Z : out stud_logic_vector(17 downto 0) -- Output(18bit)
);
end SQRT36 ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of SQRT36 is
begin
--------------------------------
-- Square Root
--------------------------------
SQRT_LOOP : process( X )
variable R : std_logic_vector(35 downto 0); -- Remain
variable S : std_logic_vector(17 downto 0); -- Result
variable T : std_logic_vector(35 downto 0); -- Calclate Value
begin
-- Initialize value
R := X ;
-- Calculate MSB(bit 17)
if( R(35 downto 34) >= "01" ) then
S(17) := '1' ;
R(35 downto 34) := R(35 downto 34) - "01" ;
else
S(17) := '0' ;
R(35 downto 34) := R(35 downto 34) ;
end if;
-- Calculate 2nd bit(bit 16)
T(35 downto 32) := '0' & S(17) & "01" ;
if( R(35 downto 32) >= T(35 downto 32) ) then
S(16) := '1' ;
R(35 downto 32) := R(35 downto 32) - T(35 downto 32) ;
else
S(16) := '0' ;
end if;
-- Calculate 3rd bit(bit 15)
T(35 downto 30) := '0' & T(35 downto 34) & S(16) & "01" ;
if( R(35 downto 30) >= T(35 downto 30) ) then
S(15) := '1' ;
R(35 downto 30) := R(35 downto 30) - T(35 downto 30) ;
else
S(15) := '0' ;
end if;
-- Calculate 4th bit(bit 14)
T(35 downto 28) := '0' & T(35 downto 32) & S(15) & "01" ;
if( R(35 downto 28) >= T(35 downto 28) ) then
S(14) := '1' ;
R(35 downto 28) := R(35 downto 28) - T(35 downto 28) ;
else
S(14) := '0' ;
end if;
-- Calculate bit 13
T(35 downto 26) := '0' & T(35 downto 30) & S(14) & "01" ;
if( R(35 downto 26) >= T(35 downto 26) ) then
S(13) := '1' ;
R(35 downto 26) := R(35 downto 26) - T(35 downto 26) ;
else
S(13) := '0' ;
end if;
-- Calculate bit 12
T(35 downto 24) := '0' & T(35 downto 28) & S(13) & "01" ;
if( R(35 downto 24) >= T(35 downto 24) ) then
S(12) := '1' ;
R(35 downto 24) := R(35 downto 24) - T(35 downto 24) ;
else
S(12) := '0' ;
end if;
-- Calculate bit 11
T(35 downto 22) := '0' & T(35 downto 26) & S(12) & "01" ;
if( R(35 downto 22) >= T(35 downto 22) ) then
S(11) := '1' ;
R(35 downto 22) := R(35 downto 22) - T(35 downto 22) ;
else
S(11) := '0' ;
end if;
-- Calculate bit 10
T(35 downto 20) := '0' & T(35 downto 24) & S(11) & "01" ;
if( R(35 downto 20) >= T(35 downto 20) ) then
S(10) := '1' ;
R(35 downto 20) := R(35 downto 20) - T(35 downto 20) ;
else
S(10) := '0' ;
end if;
-- Calculate bit 9
T(35 downto 18) := '0' & T(35 downto 22) & S(10) & "01" ;
if( R(35 downto 18) >= T(35 downto 18) ) then
S(9) := '1' ;
R(35 downto 18) := R(35 downto 18) - T(35 downto 18) ;
else
S(9) := '0' ;
end if;
-- Calculate bit 8
T(35 downto 16) := '0' & T(35 downto 20) & S(9) & "01" ;
if( R(35 downto 16) >= T(35 downto 16) ) then
S(8) := '1' ;
R(35 downto 16) := R(35 downto 16) - T(35 downto 16) ;
else
S(8) := '0' ;
end if;
-- Calculate bit 7
T(35 downto 14) := '0' & T(35 downto 18) & S(8) & "01" ;
if( R(35 downto 14) >= T(35 downto 14) ) then
S(7) := '1' ;
R(35 downto 14) := R(35 downto 14) - T(35 downto 14) ;
else
S(7) := '0' ;
end if;
-- Calculate bit 6
T(35 downto 12) := '0' & T(35 downto 16) & S(7) & "01" ;
if( R(35 downto 12) >= T(35 downto 12) ) then
S(6) := '1' ;
R(35 downto 12) := R(35 downto 12) - T(35 downto 12) ;
else
S(6) := '0' ;
end if;
-- Calculate bit 5
T(35 downto 10) := '0' & T(35 downto 14) & S(6) & "01" ;
if( R(35 downto 10) >= T(35 downto 10) ) then
S(5) := '1' ;
R(35 downto 10) := R(35 downto 10) - T(35 downto 10) ;
else
S(5) := '0' ;
end if;
-- Calculate bit 4
T(35 downto 8) := '0' & T(35 downto 12) & S(5) & "01" ;
if( R(35 downto 8) >= T(35 downto 8) ) then
S(4) := '1' ;
R(35 downto 8) := R(35 downto 8) - T(35 downto 8) ;
else
S(4) := '0' ;
end if;
-- Calculate bit 3
T(35 downto 6) := '0' & T(35 downto 10) & S(4) & "01" ;
if( R(35 downto 6) >= T(35 downto 6) ) then
S(3) := '1' ;
R(35 downto 6) := R(35 downto 6) - T(35 downto 6) ;
else
S(3) := '0' ;
end if;
-- Calculate bit 2
T(35 downto 4) := '0' & T(35 downto 8) & S(3) & "01" ;
if( R(35 downto 4) >= T(35 downto 4) ) then
S(2) := '1' ;
R(35 downto 4) := R(35 downto 4) - T(35 downto 4) ;
else
S(2) := '0' ;
end if;
-- Calculate bit 1
T(35 downto 2) := '0' & T(35 downto 6) & S(2) & "01" ;
if( R(35 downto 2) >= T(35 downto 2) ) then
S(1) := '1' ;
R(35 downto 2) := R(35 downto 2) - T(35 downto 2) ;
else
S(1) := '0' ;
end if;
-- Calculate bit 0
T(35 downto 0) := '0' & T(35 downto 4) & S(1) & "01" ;
if( R(35 downto 0) >= T(35 downto 0) ) then
S(0) := '1' ;
R(35 downto 0) := R(35 downto 0) - T(35 downto 0) ;
else
S(0) := '0' ;
end if;
-- Result
Z <= S ;
end process ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// File SQRT36.vhd --
// Entity SQRT36 --
// rev date coded contents --
// 001 98/06/10 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module sqrt36 ( x, z );
input [35:0] x ;
output [17:0] z ;
reg [35:0] sqrt_loop__r;
reg [17:0] sqrt_loop__s;
reg [35:0] sqrt_loop__t;
reg [17:0] z;
always @ (x ) begin
sqrt_loop__r = x;
if ((sqrt_loop__r[35:34] >= 2'b01))
begin
sqrt_loop__s[17] = 1'b1;
sqrt_loop__r[35:34] = (sqrt_loop__r[35:34] - 2'b01);
end
else
begin
sqrt_loop__s[17] = 1'b0;
sqrt_loop__r[35:34] = sqrt_loop__r[35:34];
end
sqrt_loop__t[35:32] = {{1'b0,sqrt_loop__s[17]},2'b01};
if ((sqrt_loop__r[35:32] >= sqrt_loop__t[35:32]))
begin
sqrt_loop__s[16] = 1'b1;
sqrt_loop__r[35:32] = (sqrt_loop__r[35:32] - sqrt_loop__t[35:32]);
end
else
sqrt_loop__s[16] = 1'b0;
sqrt_loop__t[35:30] = {{{1'b0,sqrt_loop__t[35:34]},sqrt_loop__s[16]},2'b01};
if ((sqrt_loop__r[35:30] >= sqrt_loop__t[35:30]))
begin
sqrt_loop__s[15] = 1'b1;
sqrt_loop__r[35:30] = (sqrt_loop__r[35:30] - sqrt_loop__t[35:30]);
end
else
sqrt_loop__s[15] = 1'b0;
sqrt_loop__t[35:28] = {{{1'b0,sqrt_loop__t[35:32]},sqrt_loop__s[15]},2'b01};
if ((sqrt_loop__r[35:28] >= sqrt_loop__t[35:28]))
begin
sqrt_loop__s[14] = 1'b1;
sqrt_loop__r[35:28] = (sqrt_loop__r[35:28] - sqrt_loop__t[35:28]);
end
else
sqrt_loop__s[14] = 1'b0;
sqrt_loop__t[35:26] = {{{1'b0,sqrt_loop__t[35:30]},sqrt_loop__s[14]},2'b01};
if ((sqrt_loop__r[35:26] >= sqrt_loop__t[35:26]))
begin
sqrt_loop__s[13] = 1'b1;
sqrt_loop__r[35:26] = (sqrt_loop__r[35:26] - sqrt_loop__t[35:26]);
end
else
sqrt_loop__s[13] = 1'b0;
sqrt_loop__t[35:24] = {{{1'b0,sqrt_loop__t[35:28]},sqrt_loop__s[13]},2'b01};
if ((sqrt_loop__r[35:24] >= sqrt_loop__t[35:24]))
begin
sqrt_loop__s[12] = 1'b1;
sqrt_loop__r[35:24] = (sqrt_loop__r[35:24] - sqrt_loop__t[35:24]);
end
else
sqrt_loop__s[12] = 1'b0;
sqrt_loop__t[35:22] = {{{1'b0,sqrt_loop__t[35:26]},sqrt_loop__s[12]},2'b01};
if ((sqrt_loop__r[35:22] >= sqrt_loop__t[35:22]))
begin
sqrt_loop__s[11] = 1'b1;
sqrt_loop__r[35:22] = (sqrt_loop__r[35:22] - sqrt_loop__t[35:22]);
end
else
sqrt_loop__s[11] = 1'b0;
sqrt_loop__t[35:20] = {{{1'b0,sqrt_loop__t[35:24]},sqrt_loop__s[11]},2'b01};
if ((sqrt_loop__r[35:20] >= sqrt_loop__t[35:20]))
begin
sqrt_loop__s[10] = 1'b1;
sqrt_loop__r[35:20] = (sqrt_loop__r[35:20] - sqrt_loop__t[35:20]);
end
else
sqrt_loop__s[10] = 1'b0;
sqrt_loop__t[35:18] = {{{1'b0,sqrt_loop__t[35:22]},sqrt_loop__s[10]},2'b01};
if ((sqrt_loop__r[35:18] >= sqrt_loop__t[35:18]))
begin
sqrt_loop__s[9] = 1'b1;
sqrt_loop__r[35:18] = (sqrt_loop__r[35:18] - sqrt_loop__t[35:18]);
end
else
sqrt_loop__s[9] = 1'b0;
sqrt_loop__t[35:16] = {{{1'b0,sqrt_loop__t[35:20]},sqrt_loop__s[9]},2'b01};
if ((sqrt_loop__r[35:16] >= sqrt_loop__t[35:16]))
begin
sqrt_loop__s[8] = 1'b1;
sqrt_loop__r[35:16] = (sqrt_loop__r[35:16] - sqrt_loop__t[35:16]);
end
else
sqrt_loop__s[8] = 1'b0;
sqrt_loop__t[35:14] = {{{1'b0,sqrt_loop__t[35:18]},sqrt_loop__s[8]},2'b01};
if ((sqrt_loop__r[35:14] >= sqrt_loop__t[35:14]))
begin
sqrt_loop__s[7] = 1'b1;
sqrt_loop__r[35:14] = (sqrt_loop__r[35:14] - sqrt_loop__t[35:14]);
end
else
sqrt_loop__s[7] = 1'b0;
sqrt_loop__t[35:12] = {{{1'b0,sqrt_loop__t[35:16]},sqrt_loop__s[7]},2'b01};
if ((sqrt_loop__r[35:12] >= sqrt_loop__t[35:12]))
begin
sqrt_loop__s[6] = 1'b1;
sqrt_loop__r[35:12] = (sqrt_loop__r[35:12] - sqrt_loop__t[35:12]);
end
else
sqrt_loop__s[6] = 1'b0;
sqrt_loop__t[35:10] = {{{1'b0,sqrt_loop__t[35:14]},sqrt_loop__s[6]},2'b01};
if ((sqrt_loop__r[35:10] >= sqrt_loop__t[35:10]))
begin
sqrt_loop__s[5] = 1'b1;
sqrt_loop__r[35:10] = (sqrt_loop__r[35:10] - sqrt_loop__t[35:10]);
end
else
sqrt_loop__s[5] = 1'b0;
sqrt_loop__t[35:8] = {{{1'b0,sqrt_loop__t[35:12]},sqrt_loop__s[5]},2'b01};
if ((sqrt_loop__r[35:8] >= sqrt_loop__t[35:8]))
begin
sqrt_loop__s[4] = 1'b1;
sqrt_loop__r[35:8] = (sqrt_loop__r[35:8] - sqrt_loop__t[35:8]);
end
else
sqrt_loop__s[4] = 1'b0;
sqrt_loop__t[35:6] = {{{1'b0,sqrt_loop__t[35:10]},sqrt_loop__s[4]},2'b01};
if ((sqrt_loop__r[35:6] >= sqrt_loop__t[35:6]))
begin
sqrt_loop__s[3] = 1'b1;
sqrt_loop__r[35:6] = (sqrt_loop__r[35:6] - sqrt_loop__t[35:6]);
end
else
sqrt_loop__s[3] = 1'b0;
sqrt_loop__t[35:4] = {{{1'b0,sqrt_loop__t[35:8]},sqrt_loop__s[3]},2'b01};
if ((sqrt_loop__r[35:4] >= sqrt_loop__t[35:4]))
begin
sqrt_loop__s[2] = 1'b1;
sqrt_loop__r[35:4] = (sqrt_loop__r[35:4] - sqrt_loop__t[35:4]);
end
else
sqrt_loop__s[2] = 1'b0;
sqrt_loop__t[35:2] = {{{1'b0,sqrt_loop__t[35:6]},sqrt_loop__s[2]},2'b01};
if ((sqrt_loop__r[35:2] >= sqrt_loop__t[35:2]))
begin
sqrt_loop__s[1] = 1'b1;
sqrt_loop__r[35:2] = (sqrt_loop__r[35:2] - sqrt_loop__t[35:2]);
end
else
sqrt_loop__s[1] = 1'b0;
sqrt_loop__t[35:0] = {{{1'b0,sqrt_loop__t[35:4]},sqrt_loop__s[1]},2'b01};
if ((sqrt_loop__r[35:0] >= sqrt_loop__t[35:0]))
begin
sqrt_loop__s[0] = 1'b1;
sqrt_loop__r[35:0] = (sqrt_loop__r[35:0] - sqrt_loop__t[35:0]);
end
else
sqrt_loop__s[0] = 1'b0;
z <= sqrt_loop__s;
end //always
endmodule
|
------------------------------------------------------------------------
-- File DIV18.vhd --
-- Entity DIV18 --
-- rev date coded contents --
-- 001 98/06/23 ueno Make Original --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_arith.all;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity DIV18 is
port(
X : in std_logic_vector(17 downto 0) ; -- Input(18bit)
Y : in std_logic_vector(17 downto 0) ; -- Input(18bit)
C : out std_logic ; -- OverFlow Flag
Z : out std_logic_vector(17 downto 0) -- Output(18bit)
);
end DIV18 ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of DIV18 is
begin
--------------------------------
-- X divide by Y (X < Y)
--------------------------------
DIVIDE_LOOP : process( X, Y )
variable R : std_logic_vector(19 downto 0); -- Remain
variable S : std_logic_vector(17 downto 0); -- Result
variable T : std_logic_vector(19 downto 0); -- Temporaly
begin
if( X < Y ) then
-- Initialize value
R := '0' & X & '0' ; -- R = 2 * X
T := "00" & Y ; -- T = Y
for i in 17 downto 0 loop
if( R >= T ) then
S(i) := '1' ;
R := R - T ;
else
S(i) := '0' ;
end if ;
R := R(18 downto 0) & '0' ;
end loop ;
-- Result
Z <= S ;
C <= '0' ;
else
C <= '1' ;
Z <= "000000000000000000" ;
end if ;
end process ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// File DIV18.vhd --
// Entity DIV18 --
// rev date coded contents --
// 001 98/06/23 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module div18 ( x, y, c, z );
input [17:0] x ;
input [17:0] y ;
output c;
output [17:0] z ;
reg [19:0] divide_loop__r;
reg [17:0] divide_loop__s;
reg [19:0] divide_loop__t;
reg c;
reg [17:0] z;
always @ (x or y ) begin
if ((x < y))
begin
divide_loop__r = {{1'b0,x},1'b0};
divide_loop__t = {2'b00,y};
begin :Block_Name_1
integer i;
for (i=17;i>=0;i=i-1) begin
begin
if ((divide_loop__r >= divide_loop__t))
begin
divide_loop__s[i] = 1'b1;
divide_loop__r = (divide_loop__r - divide_loop__t);
end
else
divide_loop__s[i] = 1'b0;
divide_loop__r = {divide_loop__r[18:0],1'b0};
end
end //for
end //end Block
z <= divide_loop__s;
c <= 1'b0;
end
else
begin
c <= 1'b1;
z <= 18'b000000000000000000;
end
end //always
endmodule
|
------------------------------------------------------------------------
-- Title Reverse Square-Root (1/sqr(X)) --
-- File RSQRT.vhd --
-- Entity RSQRT --
-- rev date coded contents --
-- 001 98/11/05 ueno Make Original --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity RSQRT is
port(
X : in std_logic_vector(19 downto 0) ; -- Input(20bit)
ZN : out std_logic_vector(3 downto 0) ; -- Exp(4bit)
ZM : out std_logic_vector(19 downto 0) -- Man(20bit)
);
end RSQRT ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of RSQRT is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal A : std_logic_vector(9 downto 0) ; --
constant CONSA : std_logic_vector(9 downto 0) := "1000000111" ; -- 2.02734375
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal B : std_logic_vector(15 downto 0) ; --
--
-- 3rd stages
-- 26bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXXXX
signal C : std_logic_vector(25 downto 0) ; --
--
-- Constant Value
constant CONSX : std_logic_vector(31 downto 0) := "11000000000000000000000000000000" ; -- 3.0
--
--
-- 0.XXXXXXXX
signal M : std_logic_vector(19 downto 0) ; -- Mantissa
signal N : std_logic_vector(3 downto 0) ; -- Expornent
begin
--------------------------------
-- Reverse Square-Root Argolizm
--
-- X = m x 4^n (m = 0.25~0.999999)
-- Z = 1/sqrt(X) = sqrt(m)/m x 2^-n
-- ^^^^^^^^^ |
-- ZM ZN
-- --1st stage (3.16bit)
-- a = (2.0275551-m) -- a = 1.78~1.02
-- --2nd stage (5.70bit) : 1000 LCs
-- b1 = (a*a) -- b1 = +3.17~+1.04
-- b2 = (m*b1) -- b2 = +0.813~+1.0208
-- b3 = (3-b2)/2 -- b3 = +0.99~+1.094
-- b4 = a*b3 -- b4 = +1.00~+1.98
-- b = b4
-- --3nd stage (10.82bit) : 2500 LCs
-- c1 = (b*b) -- c1 = +3.92~+1.00
-- c2 = (m*c1) -- c2 = +0.99~+1.01
-- c3 = (3-c2)/2 -- c3 = +0.99~+1.01
-- c4 = b*c3 -- c4 = +1.00~+1.99
-- c = c4
-- --4th stage (21.06bit) : ???? LCs
-- d1 = (c*c) -- d1 = +3.98~+1.00
-- d2 = (m*d1) -- d2 = +0.99~+1.01
-- d3 = (3-d2)/2 -- d3 = +0.99~+1.01
-- d4 = c*d3 -- d4 = +1.00~+1.99
-- d = d4
--
-- ZM = g3
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize --
-----------------------------------------------------------
RSQRT_INIT : process( X )
begin
if( X(19 downto 0) = "00000000000000000000" ) then
M <= (others=>'0') ;
N <= (others=>'0') ;
else
-- Generate M,N
if( X(19 downto 2) = "000000000000000000" ) then
M <= X(1 downto 0) & "000000000000000000" ;
N <= "0001" ;
elsif( X(19 downto 4) = "0000000000000000" ) then
M <= X(3 downto 0) & "0000000000000000" ;
N <= "0010" ;
elsif( X(19 downto 6) = "00000000000000" ) then
M <= X(5 downto 0) & "00000000000000" ;
N <= "0011" ;
elsif( X(19 downto 8) = "000000000000" ) then
M <= X(7 downto 0) & "000000000000" ;
N <= "0100" ;
elsif( X(19 downto 10) = "0000000000" ) then
M <= X(9 downto 0) & "0000000000" ;
N <= "0101" ;
elsif( X(19 downto 12) = "00000000" ) then
M <= X(11 downto 0) & "00000000" ;
N <= "0110" ;
elsif( X(19 downto 14) = "000000" ) then
M <= X(13 downto 0) & "000000" ;
N <= "0111" ;
elsif( X(19 downto 16) = "0000" ) then
M <= X(15 downto 0) & "0000" ;
N <= "1000" ;
elsif( X(19 downto 18) = "00" ) then
M <= X(17 downto 0) & "00" ;
N <= "1001" ;
else
M <= X ;
N <= "1010" ;
end if ;
end if ;
end process ;
-----------------------------------------------------------
-- 1st stage --
-----------------------------------------------------------
RSQRT_1ST : process( M )
begin
if( M = "00000000000000000000" ) then
A <= (others=>'0') ;
else
-- A = 2.03-M
A <= CONSA - ("00" & M(19 downto 12)) ;
end if ;
end process ;
-----------------------------------------------------------
-- 2nd stage --
-----------------------------------------------------------
RSQRT_1ND : process( A )
variable B1 : std_logic_vector(17 downto 0); -- A(9bit)*A(9bit)
variable B2 : std_logic_vector(16 downto 0); -- M(8bit)*B1(9bit)
variable B3 : std_logic_vector(10 downto 0); -- 3-B2(11bit)
variable B4 : std_logic_vector(19 downto 0); -- A(9bit)*B3(11bit)
begin
if( A = "0000000000" ) then
B <= (others=>'0') ;
else
B1 := A(8 downto 0) * A(8 downto 0) ;
B2 := B1(17 downto 9) * M(19 downto 12) ;
B3 := CONSX(31 downto 21) - B2(16 downto 6) ;
B4 := B3 * A(8 downto 0) ;
B <= B4(19 downto 4) ;
end if ;
end process ;
-----------------------------------------------------------
-- 3rd stage --
-----------------------------------------------------------
RSQRT_3RD : process( B )
variable C1 : std_logic_vector(29 downto 0); -- B(15bit)*B(15bit)
variable C2 : std_logic_vector(31 downto 0); -- M(16bit)*C1(16bit)
variable C3 : std_logic_vector(18 downto 0); -- 3-C2(19bit)
variable C4 : std_logic_vector(33 downto 0); -- B(15bit)*C3(19bit)
begin
if( B = "0000000000000000" ) then
C <= (others=>'0') ;
else
C1 := B(14 downto 0) * B(14 downto 0) ;
C2 := C1(29 downto 14) * M(19 downto 4) ;
C3 := CONSX(31 downto 13) - C2(31 downto 13) ;
C4 := C3 * B(14 downto 0) ;
C <= C4(33 downto 8) ;
end if ;
end process ;
ZN <= N ;
--ZM <= A & "00000000000" ;
--ZM <= B & "0000" ;
ZM <= C(24 downto 5) ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// Title Reverse Square-Root (1/sqr(X)) --
// File RSQRT.vhd --
// Entity RSQRT --
// rev date coded contents --
// 001 98/11/05 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module rsqrt ( x, zn, zm );
input [19:0] x ;
output [3:0] zn ;
output [19:0] zm ;
reg [17:0] rsqrt_1nd__b1;
reg [16:0] rsqrt_1nd__b2;
reg [10:0] rsqrt_1nd__b3;
reg [19:0] rsqrt_1nd__b4;
reg [29:0] rsqrt_3rd__c1;
reg [31:0] rsqrt_3rd__c2;
reg [18:0] rsqrt_3rd__c3;
reg [33:0] rsqrt_3rd__c4;
reg [9:0] a;
parameter [9:0] consa=10'b1000000111;
reg [15:0] b;
reg [25:0] c;
parameter [31:0] consx=32'b11000000000000000000000000000000;
reg [19:0] m;
reg [3:0] n;
wire [3:0] zn;
wire [19:0] zm;
always @ (x ) begin
if ((x[19:0] === 20'b00000000000000000000))
begin
m <= {(19-0+1- 0){1'b0}};
n <= {(3-0+1- 0){1'b0}};
end
else
begin
if ((x[19:2] === 18'b000000000000000000))
begin
m <= {x[1:0],18'b000000000000000000};
n <= 4'b0001;
end
else if ((x[19:4] === 16'b0000000000000000))
begin
m <= {x[3:0],16'b0000000000000000};
n <= 4'b0010;
end
else if ((x[19:6] === 14'b00000000000000))
begin
m <= {x[5:0],14'b00000000000000};
n <= 4'b0011;
end
else if ((x[19:8] === 12'b000000000000))
begin
m <= {x[7:0],12'b000000000000};
n <= 4'b0100;
end
else if ((x[19:10] === 10'b0000000000))
begin
m <= {x[9:0],10'b0000000000};
n <= 4'b0101;
end
else if ((x[19:12] === 8'b00000000))
begin
m <= {x[11:0],8'b00000000};
n <= 4'b0110;
end
else if ((x[19:14] === 6'b000000))
begin
m <= {x[13:0],6'b000000};
n <= 4'b0111;
end
else if ((x[19:16] === 4'b0000))
begin
m <= {x[15:0],4'b0000};
n <= 4'b1000;
end
else if ((x[19:18] === 2'b00))
begin
m <= {x[17:0],2'b00};
n <= 4'b1001;
end
else
begin
m <= x;
n <= 4'b1010;
end
end
end //always
always @ (m ) begin
if ((m === 20'b00000000000000000000))
a <= {(9-0+1- 0){1'b0}};
else
a <= (consa - {2'b00,m[19:12]});
end //always
always @ (a ) begin
if ((a === 10'b0000000000))
b <= {(15-0+1- 0){1'b0}};
else
begin
rsqrt_1nd__b1 = (a[8:0] * a[8:0]);
rsqrt_1nd__b2 = (rsqrt_1nd__b1[17:9] * m[19:12]);
rsqrt_1nd__b3 = (consx[31:21] - rsqrt_1nd__b2[16:6]);
rsqrt_1nd__b4 = (rsqrt_1nd__b3 * a[8:0]);
b <= rsqrt_1nd__b4[19:4];
end
end //always
always @ (b ) begin
if ((b === 16'b0000000000000000))
c <= {(25-0+1- 0){1'b0}};
else
begin
rsqrt_3rd__c1 = (b[14:0] * b[14:0]);
rsqrt_3rd__c2 = (rsqrt_3rd__c1[29:14] * m[19:4]);
rsqrt_3rd__c3 = (consx[31:13] - rsqrt_3rd__c2[31:13]);
rsqrt_3rd__c4 = (rsqrt_3rd__c3 * b[14:0]);
c <= rsqrt_3rd__c4[33:8];
end
end //always
assign {zn}=n;
assign {zm}=c[24:5];
endmodule
|
------------------------------------------------------------------------
-- Title Reverse Square-Root (1/sqr(X)) --
-- File RSQRT.vhd --
-- Entity RSQRT --
-- rev date coded contents --
-- 001 98/11/05 ueno Make Original --
-- 002 98/11/10 ueno 4th stage up --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity RSQRT is
port(
X : in std_logic_vector(19 downto 0) ; -- Input(20bit)
ZN : out std_logic_vector(3 downto 0) ; -- Exp(4bit)
ZM : out std_logic_vector(19 downto 0) -- Man(20bit)
);
end RSQRT ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of RSQRT is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal A : std_logic_vector(9 downto 0) ; --
constant CONSA : std_logic_vector(9 downto 0) := "1000000111" ; -- 2.02734375
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal B : std_logic_vector(15 downto 0) ; --
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal C : std_logic_vector(23 downto 0) ; --
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal D : std_logic_vector(23 downto 0) ; --
--
-- Constant Value
constant CONSX : std_logic_vector(31 downto 0) := "11000000000000000000000000000000" ; -- 3.0
--
--
-- 0.XXXXXXXX
signal M : std_logic_vector(19 downto 0) ; -- Mantissa
signal N : std_logic_vector(3 downto 0) ; -- Expornent
begin
--------------------------------
-- Reverse Square-Root Argolizm
--
-- X = m x 4^n (m = 0.25~0.999999)
-- Z = 1/sqrt(X) = sqrt(m)/m x 2^-n
-- ^^^^^^^^^ |
-- ZM ZN
-- --1st stage (3.16bit)
-- a = (2.0275551-m) -- a = 1.78~1.02
-- --2nd stage (5.70bit) : 1000 LCs
-- b1 = (a*a) -- b1 = +3.17~+1.04
-- b2 = (m*b1) -- b2 = +0.813~+1.0208
-- b3 = (3-b2)/2 -- b3 = +0.99~+1.094
-- b4 = a*b3 -- b4 = +1.00~+1.98
-- b = b4
-- --3nd stage (10.82bit) : 2500 LCs
-- c1 = (b*b) -- c1 = +3.92~+1.00
-- c2 = (m*c1) -- c2 = +0.99~+1.01
-- c3 = (3-c2)/2 -- c3 = +0.99~+1.01
-- c4 = b*c3 -- c4 = +1.00~+1.99
-- c = c4
-- --4th stage (21.06bit) : 5000 LCs
-- d1 = (c*c) -- d1 = +3.98~+1.00
-- d2 = (m*d1) -- d2 = +0.99~+1.01
-- d3 = (3-d2)/2 -- d3 = +0.99~+1.01
-- d4 = c*d3 -- d4 = +1.00~+1.99
-- d = d4
--
-- ZM = g3
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize --
-----------------------------------------------------------
RSQRT_INIT : process( X )
begin
if( X(19 downto 0) = "00000000000000000000" ) then
M <= (others=>'0') ;
N <= (others=>'0') ;
else
-- Generate M,N
if( X(19 downto 2) = "000000000000000000" ) then
M <= X(1 downto 0) & "000000000000000000" ;
N <= "0001" ;
elsif( X(19 downto 4) = "0000000000000000" ) then
M <= X(3 downto 0) & "0000000000000000" ;
N <= "0010" ;
elsif( X(19 downto 6) = "00000000000000" ) then
M <= X(5 downto 0) & "00000000000000" ;
N <= "0011" ;
elsif( X(19 downto 8) = "000000000000" ) then
M <= X(7 downto 0) & "000000000000" ;
N <= "0100" ;
elsif( X(19 downto 10) = "0000000000" ) then
M <= X(9 downto 0) & "0000000000" ;
N <= "0101" ;
elsif( X(19 downto 12) = "00000000" ) then
M <= X(11 downto 0) & "00000000" ;
N <= "0110" ;
elsif( X(19 downto 14) = "000000" ) then
M <= X(13 downto 0) & "000000" ;
N <= "0111" ;
elsif( X(19 downto 16) = "0000" ) then
M <= X(15 downto 0) & "0000" ;
N <= "1000" ;
elsif( X(19 downto 18) = "00" ) then
M <= X(17 downto 0) & "00" ;
N <= "1001" ;
else
M <= X ;
N <= "1010" ;
end if ;
end if ;
end process ;
-----------------------------------------------------------
-- 1st stage --
-----------------------------------------------------------
RSQRT_1ST : process( M )
begin
if( M = "00000000000000000000" ) then
A <= (others=>'0') ;
else
-- A = 2.03-M
A <= CONSA - ("00" & M(19 downto 12)) ;
end if ;
end process ;
-----------------------------------------------------------
-- 2nd stage --
-----------------------------------------------------------
RSQRT_1ND : process( M, A )
variable B1 : std_logic_vector(17 downto 0); -- A(9bit)*A(9bit)
variable B2 : std_logic_vector(16 downto 0); -- M(8bit)*B1(9bit)
variable B3 : std_logic_vector(10 downto 0); -- 3-B2(11bit)
variable B4 : std_logic_vector(19 downto 0); -- A(9bit)*B3(11bit)
begin
if( A = "0000000000" ) then
B <= (others=>'0') ;
else
B1 := A(8 downto 0) * A(8 downto 0) ;
B2 := B1(17 downto 9) * M(19 downto 12) ;
B3 := CONSX(31 downto 21) - B2(16 downto 6) ;
B4 := B3 * A(8 downto 0) ;
B <= B4(19 downto 4) ;
end if ;
end process ;
-----------------------------------------------------------
-- 3rd stage --
-----------------------------------------------------------
RSQRT_3RD : process( M, B )
variable C1 : std_logic_vector(29 downto 0); -- B(15bit)*B(15bit)
variable C2 : std_logic_vector(31 downto 0); -- M(16bit)*C1(16bit)
variable C3 : std_logic_vector(18 downto 0); -- 3-C2(19bit)
variable C4 : std_logic_vector(33 downto 0); -- B(15bit)*C3(19bit)
begin
if( B = "0000000000000000" ) then
C <= (others=>'0') ;
else
C1 := B(14 downto 0) * B(14 downto 0) ;
C2 := C1(29 downto 14) * M(19 downto 4) ;
C3 := CONSX(31 downto 13) - C2(31 downto 13) ;
C4 := C3 * B(14 downto 0) ;
C <= C4(33 downto 10) ;
end if ;
end process ;
-----------------------------------------------------------
-- 4th stage --
-----------------------------------------------------------
RSQRT_4TH : process( M, C )
variable D1 : std_logic_vector(39 downto 0); -- C(20bit)*C(20bit)
variable D2 : std_logic_vector(39 downto 0); -- M(20bit)*D1(20bit)
variable D3 : std_logic_vector(23 downto 0); -- 3-D2(24bit)
variable D4 : std_logic_vector(43 downto 0); -- C(20bit)*D3(24bit)
begin
if( C = "000000000000000000000000" ) then
D <= (others=>'0') ;
else
D1 := C(22 downto 3) * C(22 downto 3) ;
D2 := D1(39 downto 20) * M(19 downto 0) ;
D3 := CONSX(31 downto 8) - D2(39 downto 16) ;
D4 := D3 * C(22 downto 3) ;
D <= D4(43 downto 20) ;
end if ;
end process ;
ZN <= N ;
--ZM <= A & "00000000000" ;
--ZM <= B & "0000" ;
--ZM <= C(22 downto 3) ;
ZM <= D(22 downto 3) ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// Title Reverse Square-Root (1/sqr(X)) --
// File RSQRT.vhd --
// Entity RSQRT --
// rev date coded contents --
// 001 98/11/05 ueno Make Original --
// 002 98/11/10 ueno 4th stage up --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module rsqrt ( x, zn, zm );
input [19:0] x ;
output [3:0] zn ;
output [19:0] zm ;
reg [17:0] rsqrt_1nd__b1;
reg [16:0] rsqrt_1nd__b2;
reg [10:0] rsqrt_1nd__b3;
reg [19:0] rsqrt_1nd__b4;
reg [29:0] rsqrt_3rd__c1;
reg [31:0] rsqrt_3rd__c2;
reg [18:0] rsqrt_3rd__c3;
reg [33:0] rsqrt_3rd__c4;
reg [39:0] rsqrt_4th__d1;
reg [39:0] rsqrt_4th__d2;
reg [23:0] rsqrt_4th__d3;
reg [43:0] rsqrt_4th__d4;
reg [9:0] a;
parameter [9:0] consa=10'b1000000111;
reg [15:0] b;
reg [23:0] c;
reg [23:0] d;
parameter [31:0] consx=32'b11000000000000000000000000000000;
reg [19:0] m;
reg [3:0] n;
wire [3:0] zn;
wire [19:0] zm;
always @ (x ) begin
if ((x[19:0] === 20'b00000000000000000000))
begin
m <= {(19-0+1- 0){1'b0}};
n <= {(3-0+1- 0){1'b0}};
end
else
begin
if ((x[19:2] === 18'b000000000000000000))
begin
m <= {x[1:0],18'b000000000000000000};
n <= 4'b0001;
end
else if ((x[19:4] === 16'b0000000000000000))
begin
m <= {x[3:0],16'b0000000000000000};
n <= 4'b0010;
end
else if ((x[19:6] === 14'b00000000000000))
begin
m <= {x[5:0],14'b00000000000000};
n <= 4'b0011;
end
else if ((x[19:8] === 12'b000000000000))
begin
m <= {x[7:0],12'b000000000000};
n <= 4'b0100;
end
else if ((x[19:10] === 10'b0000000000))
begin
m <= {x[9:0],10'b0000000000};
n <= 4'b0101;
end
else if ((x[19:12] === 8'b00000000))
begin
m <= {x[11:0],8'b00000000};
n <= 4'b0110;
end
else if ((x[19:14] === 6'b000000))
begin
m <= {x[13:0],6'b000000};
n <= 4'b0111;
end
else if ((x[19:16] === 4'b0000))
begin
m <= {x[15:0],4'b0000};
n <= 4'b1000;
end
else if ((x[19:18] === 2'b00))
begin
m <= {x[17:0],2'b00};
n <= 4'b1001;
end
else
begin
m <= x;
n <= 4'b1010;
end
end
end //always
always @ (m ) begin
if ((m === 20'b00000000000000000000))
a <= {(9-0+1- 0){1'b0}};
else
a <= (consa - {2'b00,m[19:12]});
end //always
always @ (m or a ) begin
if ((a === 10'b0000000000))
b <= {(15-0+1- 0){1'b0}};
else
begin
rsqrt_1nd__b1 = (a[8:0] * a[8:0]);
rsqrt_1nd__b2 = (rsqrt_1nd__b1[17:9] * m[19:12]);
rsqrt_1nd__b3 = (consx[31:21] - rsqrt_1nd__b2[16:6]);
rsqrt_1nd__b4 = (rsqrt_1nd__b3 * a[8:0]);
b <= rsqrt_1nd__b4[19:4];
end
end //always
always @ (m or b ) begin
if ((b === 16'b0000000000000000))
c <= {(23-0+1- 0){1'b0}};
else
begin
rsqrt_3rd__c1 = (b[14:0] * b[14:0]);
rsqrt_3rd__c2 = (rsqrt_3rd__c1[29:14] * m[19:4]);
rsqrt_3rd__c3 = (consx[31:13] - rsqrt_3rd__c2[31:13]);
rsqrt_3rd__c4 = (rsqrt_3rd__c3 * b[14:0]);
c <= rsqrt_3rd__c4[33:10];
end
end //always
always @ (m or c ) begin
if ((c === 24'b000000000000000000000000))
d <= {(23-0+1- 0){1'b0}};
else
begin
rsqrt_4th__d1 = (c[22:3] * c[22:3]);
rsqrt_4th__d2 = (rsqrt_4th__d1[39:20] * m[19:0]);
rsqrt_4th__d3 = (consx[31:8] - rsqrt_4th__d2[39:16]);
rsqrt_4th__d4 = (rsqrt_4th__d3 * c[22:3]);
d <= rsqrt_4th__d4[43:20];
end
end //always
assign {zn}=n;
assign {zm}=d[22:3];
endmodule
|
------------------------------------------------------------------------
-- Title Reverse X (1/X) --
-- File REVX.vhd --
-- Entity REVX --
-- rev date coded contents --
-- 001 98/11/10 ueno Make Original --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity REVX is
port(
X : in std_logic_vector(19 downto 0) ; -- Input(20bit)
ZN : out std_logic_vector(4 downto 0) ; -- Exp(5bit)
ZM : out std_logic_vector(19 downto 0) -- Man(20bit)
);
end REVX ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of REVX is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal A : std_logic_vector(9 downto 0) ; --
constant CONSA : std_logic_vector(9 downto 0) := "1100000000" ; -- 3
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal B : std_logic_vector(15 downto 0) ; --
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal C : std_logic_vector(23 downto 0) ; --
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal D : std_logic_vector(23 downto 0) ; --
--
-- Constant Value
constant CONSX : std_logic_vector(31 downto 0) := "10000000000000000000000000000000" ; -- 2.0
--
--
-- 0.XXXXXXXX
signal M : std_logic_vector(19 downto 0) ; -- Mantissa
signal N : std_logic_vector(4 downto 0) ; -- Expornent
begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- Z = 1/X = 1/m x 2^-n
-- | |
-- ZM ZN
-- --1st stage (3bit)
-- a = (3-2*m) -- a = 1~2 (3.00bit)
-- a = (723-482*m)/256 -- a = 1~2 (4.08bit)
-- --2nd stage (6bit) : xxxx LCs
-- b1 = (m*a) -- b1 = 1~1.125
-- b2 = (2-b1) -- b2 = 0.875~1
-- b3 = a*b2 -- b3 = 1~2
-- b = b3
-- --3nd stage (12bit) : xxxx LCs
-- c1 = (m*b) -- c1 = 0.98~1
-- c2 = (2-c1) -- c2 = 1~1.01
-- c3 = b*c2 -- c3 = 1~2
-- c = c4
-- --4th stage (24bit) : ???? LCs
-- d1 = (m*c) -- d1 = 0.99~1
-- d2 = (3-d1) -- d2 = 1~1.00
-- d3 = c*d2 -- d3 = 1~2
-- d = d4
--
-- ZM = d
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize --
-----------------------------------------------------------
REVX_INIT : process( X )
begin
if( X(19 downto 0) = "00000000000000000000" ) then
M <= (others=>'0') ;
N <= (others=>'0') ;
else
-- Generate M,N
if( X(19 downto 1) = "0000000000000000000" ) then
M <= X(0) & "0000000000000000000" ;
N <= "00001" ;
elsif( X(19 downto 2) = "000000000000000000" ) then
M <= X(1 downto 0) & "000000000000000000" ;
N <= "00010" ;
elsif( X(19 downto 3) = "00000000000000000" ) then
M <= X(2 downto 0) & "00000000000000000" ;
N <= "00011" ;
elsif( X(19 downto 4) = "0000000000000000" ) then
M <= X(3 downto 0) & "0000000000000000" ;
N <= "00100" ;
elsif( X(19 downto 5) = "000000000000000" ) then
M <= X(4 downto 0) & "000000000000000" ;
N <= "00101" ;
elsif( X(19 downto 6) = "00000000000000" ) then
M <= X(5 downto 0) & "00000000000000" ;
N <= "00110" ;
elsif( X(19 downto 7) = "0000000000000" ) then
M <= X(6 downto 0) & "0000000000000" ;
N <= "00111" ;
elsif( X(19 downto 8) = "000000000000" ) then
M <= X(7 downto 0) & "000000000000" ;
N <= "01000" ;
elsif( X(19 downto 9) = "00000000000" ) then
M <= X(8 downto 0) & "00000000000" ;
N <= "01001" ;
elsif( X(19 downto 10) = "0000000000" ) then
M <= X(9 downto 0) & "0000000000" ;
N <= "01010" ;
elsif( X(19 downto 11) = "000000000" ) then
M <= X(10 downto 0) & "000000000" ;
N <= "01011" ;
elsif( X(19 downto 12) = "00000000" ) then
M <= X(11 downto 0) & "00000000" ;
N <= "01100" ;
elsif( X(19 downto 13) = "0000000" ) then
M <= X(12 downto 0) & "0000000" ;
N <= "01101" ;
elsif( X(19 downto 14) = "000000" ) then
M <= X(13 downto 0) & "000000" ;
N <= "01110" ;
elsif( X(19 downto 15) = "00000" ) then
M <= X(14 downto 0) & "00000" ;
N <= "01111" ;
elsif( X(19 downto 16) = "0000" ) then
M <= X(15 downto 0) & "0000" ;
N <= "10000" ;
elsif( X(19 downto 17) = "000" ) then
M <= X(16 downto 0) & "000" ;
N <= "10001" ;
elsif( X(19 downto 18) = "00" ) then
M <= X(17 downto 0) & "00" ;
N <= "10010" ;
elsif( X(19) = '0' ) then
M <= X(18 downto 0) & '0' ;
N <= "10011" ;
else
M <= X ;
N <= "10100" ;
end if ;
end if ;
end process ;
-----------------------------------------------------------
-- 1st stage --
-----------------------------------------------------------
REVX_1ST : process( M )
begin
if( M = "00000000000000000000" ) then
A <= (others=>'0') ;
else
-- A = 3-2*M
A <= CONSA - ('0' & M(19 downto 11)) ;
end if ;
end process ;
-----------------------------------------------------------
-- 2nd stage --
-----------------------------------------------------------
REVX_1ND : process( M, A )
variable B1 : std_logic_vector(19 downto 0); -- M(10bit)*A(10bit) XX.XX....
variable B2 : std_logic_vector(11 downto 0); -- 2-B1(12bit) X.XX....
variable B3 : std_logic_vector(21 downto 0); -- A(10bit)*B2(12bit) XXX.XX....
begin
if( A = "0000000000" ) then
B <= (others=>'0') ;
else
B1 := M(19 downto 10) * A ;
B2 := CONSX(30 downto 19) - B1(18 downto 7) ;
B3 := B2 * A ;
B <= B3(20 downto 5) ;
end if ;
end process ;
-----------------------------------------------------------
-- 3rd stage --
-----------------------------------------------------------
REVX_3RD : process( M, B )
variable C1 : std_logic_vector(31 downto 0); -- M(16bit)*B(16bit) XX.XX...
variable C2 : std_logic_vector(19 downto 0); -- 2-C1(20bit) X.XX...
variable C3 : std_logic_vector(35 downto 0); -- B(16bit)*C2(20bit) XXX.XX...
begin
if( B = "0000000000000000" ) then
C <= (others=>'0') ;
else
C1 := B * M(19 downto 4) ;
C2 := CONSX(30 downto 11) - C1(30 downto 11) ;
C3 := C2 * B ;
C <= C3(34 downto 11) ;
end if ;
end process ;
-----------------------------------------------------------
-- 4th stage --
-----------------------------------------------------------
REVX_4TH : process( M, C )
variable D1 : std_logic_vector(39 downto 0); -- M(20bit)*C(20bit) XX.XX...
variable D2 : std_logic_vector(23 downto 0); -- 2-D1(24bit) X.XX...
variable D3 : std_logic_vector(43 downto 0); -- C(20bit)*D2(24bit) XXX.XX...
begin
if( C = "000000000000000000000000" ) then
D <= (others=>'0') ;
else
D1 := C(23 downto 4) * M ;
D2 := CONSX(30 downto 7) - D1(38 downto 15) ;
D3 := D2 * C(23 downto 4) ;
D <= D3(42 downto 19) ;
end if ;
end process ;
ZN <= N ;
--ZM <= A & "0000000000" ;
--ZM <= B & "0000" ;
ZM <= C(23 downto 4) ;
--ZM <= D(23 downto 4) ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// Title Reverse X (1/X) --
// File REVX.vhd --
// Entity REVX --
// rev date coded contents --
// 001 98/11/10 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module revx ( x, zn, zm );
input [19:0] x ;
output [4:0] zn ;
output [19:0] zm ;
reg [19:0] revx_1nd__b1;
reg [11:0] revx_1nd__b2;
reg [21:0] revx_1nd__b3;
reg [31:0] revx_3rd__c1;
reg [19:0] revx_3rd__c2;
reg [35:0] revx_3rd__c3;
reg [39:0] revx_4th__d1;
reg [23:0] revx_4th__d2;
reg [43:0] revx_4th__d3;
reg [9:0] a;
parameter [9:0] consa=10'b1100000000;
reg [15:0] b;
reg [23:0] c;
reg [23:0] d;
parameter [31:0] consx=32'b10000000000000000000000000000000;
reg [19:0] m;
reg [4:0] n;
wire [4:0] zn;
wire [19:0] zm;
always @ (x ) begin
if ((x[19:0] === 20'b00000000000000000000))
begin
m <= {(19-0+1- 0){1'b0}};
n <= {(4-0+1- 0){1'b0}};
end
else
begin
if ((x[19:1] === 19'b0000000000000000000))
begin
m <= {x[0],19'b0000000000000000000};
n <= 5'b00001;
end
else if ((x[19:2] === 18'b000000000000000000))
begin
m <= {x[1:0],18'b000000000000000000};
n <= 5'b00010;
end
else if ((x[19:3] === 17'b00000000000000000))
begin
m <= {x[2:0],17'b00000000000000000};
n <= 5'b00011;
end
else if ((x[19:4] === 16'b0000000000000000))
begin
m <= {x[3:0],16'b0000000000000000};
n <= 5'b00100;
end
else if ((x[19:5] === 15'b000000000000000))
begin
m <= {x[4:0],15'b000000000000000};
n <= 5'b00101;
end
else if ((x[19:6] === 14'b00000000000000))
begin
m <= {x[5:0],14'b00000000000000};
n <= 5'b00110;
end
else if ((x[19:7] === 13'b0000000000000))
begin
m <= {x[6:0],13'b0000000000000};
n <= 5'b00111;
end
else if ((x[19:8] === 12'b000000000000))
begin
m <= {x[7:0],12'b000000000000};
n <= 5'b01000;
end
else if ((x[19:9] === 11'b00000000000))
begin
m <= {x[8:0],11'b00000000000};
n <= 5'b01001;
end
else if ((x[19:10] === 10'b0000000000))
begin
m <= {x[9:0],10'b0000000000};
n <= 5'b01010;
end
else if ((x[19:11] === 9'b000000000))
begin
m <= {x[10:0],9'b000000000};
n <= 5'b01011;
end
else if ((x[19:12] === 8'b00000000))
begin
m <= {x[11:0],8'b00000000};
n <= 5'b01100;
end
else if ((x[19:13] === 7'b0000000))
begin
m <= {x[12:0],7'b0000000};
n <= 5'b01101;
end
else if ((x[19:14] === 6'b000000))
begin
m <= {x[13:0],6'b000000};
n <= 5'b01110;
end
else if ((x[19:15] === 5'b00000))
begin
m <= {x[14:0],5'b00000};
n <= 5'b01111;
end
else if ((x[19:16] === 4'b0000))
begin
m <= {x[15:0],4'b0000};
n <= 5'b10000;
end
else if ((x[19:17] === 3'b000))
begin
m <= {x[16:0],3'b000};
n <= 5'b10001;
end
else if ((x[19:18] === 2'b00))
begin
m <= {x[17:0],2'b00};
n <= 5'b10010;
end
else if ((x[19] === 1'b0))
begin
m <= {x[18:0],1'b0};
n <= 5'b10011;
end
else
begin
m <= x;
n <= 5'b10100;
end
end
end //always
always @ (m ) begin
if ((m === 20'b00000000000000000000))
a <= {(9-0+1- 0){1'b0}};
else
a <= (consa - {1'b0,m[19:11]});
end //always
always @ (m or a ) begin
if ((a === 10'b0000000000))
b <= {(15-0+1- 0){1'b0}};
else
begin
revx_1nd__b1 = (m[19:10] * a);
revx_1nd__b2 = (consx[30:19] - revx_1nd__b1[18:7]);
revx_1nd__b3 = (revx_1nd__b2 * a);
b <= revx_1nd__b3[20:5];
end
end //always
always @ (m or b ) begin
if ((b === 16'b0000000000000000))
c <= {(23-0+1- 0){1'b0}};
else
begin
revx_3rd__c1 = (b * m[19:4]);
revx_3rd__c2 = (consx[30:11] - revx_3rd__c1[30:11]);
revx_3rd__c3 = (revx_3rd__c2 * b);
c <= revx_3rd__c3[34:11];
end
end //always
always @ (m or c ) begin
if ((c === 24'b000000000000000000000000))
d <= {(23-0+1- 0){1'b0}};
else
begin
revx_4th__d1 = (c[23:4] * m);
revx_4th__d2 = (consx[30:7] - revx_4th__d1[38:15]);
revx_4th__d3 = (revx_4th__d2 * c[23:4]);
d <= revx_4th__d3[42:19];
end
end //always
assign {zn}=n;
assign {zm}=c[23:4];
endmodule
|
------------------------------------------------------------------------
-- Title Reverse X (1/X) --
-- File REVX.vhd --
-- Entity REVX --
-- rev date coded contents --
-- 001 98/11/10 ueno Make Original --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity REVX is
port(
X : in std_logic_vector(19 downto 0) ; -- Input(20bit)
ZN : out std_logic_vector(4 downto 0) ; -- Exp(5bit)
ZM : out std_logic_vector(19 downto 0) -- Man(20bit)
);
end REVX ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of REVX is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal A : std_logic_vector(9 downto 0) ; --
constant CONSA : std_logic_vector(9 downto 0) := "1100000000" ; -- 3
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal B : std_logic_vector(15 downto 0) ; --
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal C : std_logic_vector(23 downto 0) ; --
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal D : std_logic_vector(23 downto 0) ; --
--
-- Constant Value
constant CONSX : std_logic_vector(31 downto 0) := "10000000000000000000000000000000" ; -- 2.0
--
--
-- 0.XXXXXXXX
signal M : std_logic_vector(19 downto 0) ; -- Mantissa
signal N : std_logic_vector(4 downto 0) ; -- Expornent
begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- Z = 1/X = 1/m x 2^-n
-- | |
-- ZM ZN
-- --1st stage (3bit)
-- a = (3-2*m) -- a = 1~2 (3.00bit)
-- a = (723-482*m)/256 -- a = 1~2 (4.08bit)
-- --2nd stage (6bit) : xxxx LCs
-- b1 = (m*a) -- b1 = 1~1.125
-- b2 = (2-b1) -- b2 = 0.875~1
-- b3 = a*b2 -- b3 = 1~2
-- b = b3
-- --3nd stage (12bit) : xxxx LCs
-- c1 = (m*b) -- c1 = 0.98~1
-- c2 = (2-c1) -- c2 = 1~1.01
-- c3 = b*c2 -- c3 = 1~2
-- c = c4
-- --4th stage (24bit) : ???? LCs
-- d1 = (m*c) -- d1 = 0.99~1
-- d2 = (3-d1) -- d2 = 1~1.00
-- d3 = c*d2 -- d3 = 1~2
-- d = d4
--
-- ZM = d
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize --
-----------------------------------------------------------
REVX_INIT : process( X )
begin
if( X(19 downto 0) = "00000000000000000000" ) then
M <= (others=>'0') ;
N <= (others=>'0') ;
else
-- Generate M,N
if( X(19 downto 1) = "0000000000000000000" ) then
M <= X(0) & "0000000000000000000" ;
N <= "00001" ;
elsif( X(19 downto 2) = "000000000000000000" ) then
M <= X(1 downto 0) & "000000000000000000" ;
N <= "00010" ;
elsif( X(19 downto 3) = "00000000000000000" ) then
M <= X(2 downto 0) & "00000000000000000" ;
N <= "00011" ;
elsif( X(19 downto 4) = "0000000000000000" ) then
M <= X(3 downto 0) & "0000000000000000" ;
N <= "00100" ;
elsif( X(19 downto 5) = "000000000000000" ) then
M <= X(4 downto 0) & "000000000000000" ;
N <= "00101" ;
elsif( X(19 downto 6) = "00000000000000" ) then
M <= X(5 downto 0) & "00000000000000" ;
N <= "00110" ;
elsif( X(19 downto 7) = "0000000000000" ) then
M <= X(6 downto 0) & "0000000000000" ;
N <= "00111" ;
elsif( X(19 downto 8) = "000000000000" ) then
M <= X(7 downto 0) & "000000000000" ;
N <= "01000" ;
elsif( X(19 downto 9) = "00000000000" ) then
M <= X(8 downto 0) & "00000000000" ;
N <= "01001" ;
elsif( X(19 downto 10) = "0000000000" ) then
M <= X(9 downto 0) & "0000000000" ;
N <= "01010" ;
elsif( X(19 downto 11) = "000000000" ) then
M <= X(10 downto 0) & "000000000" ;
N <= "01011" ;
elsif( X(19 downto 12) = "00000000" ) then
M <= X(11 downto 0) & "00000000" ;
N <= "01100" ;
elsif( X(19 downto 13) = "0000000" ) then
M <= X(12 downto 0) & "0000000" ;
N <= "01101" ;
elsif( X(19 downto 14) = "000000" ) then
M <= X(13 downto 0) & "000000" ;
N <= "01110" ;
elsif( X(19 downto 15) = "00000" ) then
M <= X(14 downto 0) & "00000" ;
N <= "01111" ;
elsif( X(19 downto 16) = "0000" ) then
M <= X(15 downto 0) & "0000" ;
N <= "10000" ;
elsif( X(19 downto 17) = "000" ) then
M <= X(16 downto 0) & "000" ;
N <= "10001" ;
elsif( X(19 downto 18) = "00" ) then
M <= X(17 downto 0) & "00" ;
N <= "10010" ;
elsif( X(19) = '0' ) then
M <= X(18 downto 0) & '0' ;
N <= "10011" ;
else
M <= X ;
N <= "10100" ;
end if ;
end if ;
end process ;
-----------------------------------------------------------
-- 1st stage --
-----------------------------------------------------------
REVX_1ST : process( M )
begin
if( M = "00000000000000000000" ) then
A <= (others=>'0') ;
else
-- A = 3-2*M
A <= CONSA - ('0' & M(19 downto 11)) ;
end if ;
end process ;
-----------------------------------------------------------
-- 2nd stage --
-----------------------------------------------------------
REVX_1ND : process( M, A )
variable B1 : std_logic_vector(19 downto 0); -- M(10bit)*A(10bit) XX.XX....
variable B2 : std_logic_vector(11 downto 0); -- 2-B1(12bit) X.XX....
variable B3 : std_logic_vector(21 downto 0); -- A(10bit)*B2(12bit) XXX.XX....
begin
if( A = "0000000000" ) then
B <= (others=>'0') ;
else
B1 := M(19 downto 10) * A ;
B2 := CONSX(30 downto 19) - B1(18 downto 7) ;
B3 := B2 * A ;
B <= B3(20 downto 5) ;
end if ;
end process ;
-----------------------------------------------------------
-- 3rd stage --
-----------------------------------------------------------
REVX_3RD : process( M, B )
variable C1 : std_logic_vector(31 downto 0); -- M(16bit)*B(16bit) XX.XX...
variable C2 : std_logic_vector(19 downto 0); -- 2-C1(20bit) X.XX...
variable C3 : std_logic_vector(35 downto 0); -- B(16bit)*C2(20bit) XXX.XX...
begin
if( B = "0000000000000000" ) then
C <= (others=>'0') ;
else
C1 := B * M(19 downto 4) ;
C2 := CONSX(30 downto 11) - C1(30 downto 11) ;
C3 := C2 * B ;
C <= C3(34 downto 11) ;
end if ;
end process ;
-----------------------------------------------------------
-- 4th stage --
-----------------------------------------------------------
REVX_4TH : process( M, C )
variable D1 : std_logic_vector(39 downto 0); -- M(20bit)*C(20bit) XX.XX...
variable D2 : std_logic_vector(23 downto 0); -- 2-D1(24bit) X.XX...
variable D3 : std_logic_vector(43 downto 0); -- C(20bit)*D2(24bit) XXX.XX...
begin
if( C = "000000000000000000000000" ) then
D <= (others=>'0') ;
else
D1 := C(23 downto 4) * M ;
D2 := CONSX(30 downto 7) - D1(38 downto 15) ;
D3 := D2 * C(23 downto 4) ;
D <= D3(42 downto 19) ;
end if ;
end process ;
ZN <= N ;
--ZM <= A & "0000000000" ;
--ZM <= B & "0000" ;
--ZM <= C(23 downto 4) ;
ZM <= D(23 downto 4) ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// Title Reverse X (1/X) --
// File REVX.vhd --
// Entity REVX --
// rev date coded contents --
// 001 98/11/10 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module revx ( x, zn, zm );
input [19:0] x ;
output [4:0] zn ;
output [19:0] zm ;
reg [19:0] revx_1nd__b1;
reg [11:0] revx_1nd__b2;
reg [21:0] revx_1nd__b3;
reg [31:0] revx_3rd__c1;
reg [19:0] revx_3rd__c2;
reg [35:0] revx_3rd__c3;
reg [39:0] revx_4th__d1;
reg [23:0] revx_4th__d2;
reg [43:0] revx_4th__d3;
reg [9:0] a;
parameter [9:0] consa=10'b1100000000;
reg [15:0] b;
reg [23:0] c;
reg [23:0] d;
parameter [31:0] consx=32'b10000000000000000000000000000000;
reg [19:0] m;
reg [4:0] n;
wire [4:0] zn;
wire [19:0] zm;
always @ (x ) begin
if ((x[19:0] === 20'b00000000000000000000))
begin
m <= {(19-0+1- 0){1'b0}};
n <= {(4-0+1- 0){1'b0}};
end
else
begin
if ((x[19:1] === 19'b0000000000000000000))
begin
m <= {x[0],19'b0000000000000000000};
n <= 5'b00001;
end
else if ((x[19:2] === 18'b000000000000000000))
begin
m <= {x[1:0],18'b000000000000000000};
n <= 5'b00010;
end
else if ((x[19:3] === 17'b00000000000000000))
begin
m <= {x[2:0],17'b00000000000000000};
n <= 5'b00011;
end
else if ((x[19:4] === 16'b0000000000000000))
begin
m <= {x[3:0],16'b0000000000000000};
n <= 5'b00100;
end
else if ((x[19:5] === 15'b000000000000000))
begin
m <= {x[4:0],15'b000000000000000};
n <= 5'b00101;
end
else if ((x[19:6] === 14'b00000000000000))
begin
m <= {x[5:0],14'b00000000000000};
n <= 5'b00110;
end
else if ((x[19:7] === 13'b0000000000000))
begin
m <= {x[6:0],13'b0000000000000};
n <= 5'b00111;
end
else if ((x[19:8] === 12'b000000000000))
begin
m <= {x[7:0],12'b000000000000};
n <= 5'b01000;
end
else if ((x[19:9] === 11'b00000000000))
begin
m <= {x[8:0],11'b00000000000};
n <= 5'b01001;
end
else if ((x[19:10] === 10'b0000000000))
begin
m <= {x[9:0],10'b0000000000};
n <= 5'b01010;
end
else if ((x[19:11] === 9'b000000000))
begin
m <= {x[10:0],9'b000000000};
n <= 5'b01011;
end
else if ((x[19:12] === 8'b00000000))
begin
m <= {x[11:0],8'b00000000};
n <= 5'b01100;
end
else if ((x[19:13] === 7'b0000000))
begin
m <= {x[12:0],7'b0000000};
n <= 5'b01101;
end
else if ((x[19:14] === 6'b000000))
begin
m <= {x[13:0],6'b000000};
n <= 5'b01110;
end
else if ((x[19:15] === 5'b00000))
begin
m <= {x[14:0],5'b00000};
n <= 5'b01111;
end
else if ((x[19:16] === 4'b0000))
begin
m <= {x[15:0],4'b0000};
n <= 5'b10000;
end
else if ((x[19:17] === 3'b000))
begin
m <= {x[16:0],3'b000};
n <= 5'b10001;
end
else if ((x[19:18] === 2'b00))
begin
m <= {x[17:0],2'b00};
n <= 5'b10010;
end
else if ((x[19] === 1'b0))
begin
m <= {x[18:0],1'b0};
n <= 5'b10011;
end
else
begin
m <= x;
n <= 5'b10100;
end
end
end //always
always @ (m ) begin
if ((m === 20'b00000000000000000000))
a <= {(9-0+1- 0){1'b0}};
else
a <= (consa - {1'b0,m[19:11]});
end //always
always @ (m or a ) begin
if ((a === 10'b0000000000))
b <= {(15-0+1- 0){1'b0}};
else
begin
revx_1nd__b1 = (m[19:10] * a);
revx_1nd__b2 = (consx[30:19] - revx_1nd__b1[18:7]);
revx_1nd__b3 = (revx_1nd__b2 * a);
b <= revx_1nd__b3[20:5];
end
end //always
always @ (m or b ) begin
if ((b === 16'b0000000000000000))
c <= {(23-0+1- 0){1'b0}};
else
begin
revx_3rd__c1 = (b * m[19:4]);
revx_3rd__c2 = (consx[30:11] - revx_3rd__c1[30:11]);
revx_3rd__c3 = (revx_3rd__c2 * b);
c <= revx_3rd__c3[34:11];
end
end //always
always @ (m or c ) begin
if ((c === 24'b000000000000000000000000))
d <= {(23-0+1- 0){1'b0}};
else
begin
revx_4th__d1 = (c[23:4] * m);
revx_4th__d2 = (consx[30:7] - revx_4th__d1[38:15]);
revx_4th__d3 = (revx_4th__d2 * c[23:4]);
d <= revx_4th__d3[42:19];
end
end //always
assign {zn}=n;
assign {zm}=d[23:4];
endmodule
|
------------------------------------------------------------------------
-- Title Logalizm X (log(X)) --
-- File LOG.vhd --
-- Entity LOG --
-- rev date coded contents --
-- 001 98/11/17 ueno Make Original --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;
------------------------------------------------------------------------
-- entity --
------------------------------------------------------------------------
entity LOG is
port(
-- XXXXXXXXXXXXXXXXXXXX. Integer Value
X : in std_logic_vector(19 downto 0) ; -- Input(20bit)
-- XXXX.XXXXXXXXXXXXXXXX Fixed Point Value
Z : out std_logic_vector(19 downto 0) -- Output(20bit)
);
end LOG ;
------------------------------------------------------------------------
-- architecture --
------------------------------------------------------------------------
architecture RTL of LOG is
-- log(2)
-- .XXXXXXXXXXXXXXXX
constant LOG2V : std_logic_vector(15 downto 0) := "1011000101110010" ;
-- 1/2 = shift1
-- 1/3
constant CONS3 : std_logic_vector(15 downto 0) := "0101010101010101" ; -- 4bit
-- 1/4 = shift2
-- 1/5
-- 1/6 = 1/3&shift
-- 1/7
constant CONS5 : std_logic_vector(15 downto 0) := "0011001100110011" ; -- 7bit
constant CONS7 : std_logic_vector(15 downto 0) := "0010010010010010" ; -- 9bit
-- 1/8 = shift3
-- 1/9
-- 1/10 = 1/5&shift
-- 1/11
-- 1/12 = 1/3&shift2
-- 1/13
-- 1/14 = 1/7&shift2
-- 1/15
constant CONS9 : std_logic_vector(15 downto 0) := "0001110001110001" ; -- 11bit
constant CONS11 : std_logic_vector(15 downto 0) := "0001011101000101" ; -- 14bit
constant CONS13 : std_logic_vector(15 downto 0) := "0001001110110001" ; -- 16bit
constant CONS15 : std_logic_vector(15 downto 0) := "0001000100010001" ; -- 18bit
--
-- .XXXXXXXXXXXXXXXX
signal Y : std_logic_vector(15 downto 0) ; -- Log( M )
--
signal F : std_logic_vector(20 downto 0) ; -- N*log(2)
signal G : std_logic_vector(20 downto 0) ; -- temp Z
--
-- 0.XXXXXXXX
signal M : std_logic_vector(19 downto 0) ; -- Mantissa
signal N : std_logic_vector(4 downto 0) ; -- Expornent
begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- m = 1-h
-- Z = log(2)*n+log(m)
-- log(2)*n-(h+h^2/2+h^3/3+h^4/4+ ....)
--
--------------------------------
-----------------------------------------------------------
-- Initialize --
-----------------------------------------------------------
FLOT_INIT : process( X )
begin
if( X(19 downto 0) = "00000000000000000000" ) then
M <= (others=>'0') ;
N <= (others=>'0') ;
else
-- Generate M,N
if( X(19 downto 1) = "0000000000000000000" ) then
M <= X(0) & "0000000000000000000" ;
N <= "00001" ;
elsif( X(19 downto 2) = "000000000000000000" ) then
M <= X(1 downto 0) & "000000000000000000" ;
N <= "00010" ;
elsif( X(19 downto 3) = "00000000000000000" ) then
M <= X(2 downto 0) & "00000000000000000" ;
N <= "00011" ;
elsif( X(19 downto 4) = "0000000000000000" ) then
M <= X(3 downto 0) & "0000000000000000" ;
N <= "00100" ;
elsif( X(19 downto 5) = "000000000000000" ) then
M <= X(4 downto 0) & "000000000000000" ;
N <= "00101" ;
elsif( X(19 downto 6) = "00000000000000" ) then
M <= X(5 downto 0) & "00000000000000" ;
N <= "00110" ;
elsif( X(19 downto 7) = "0000000000000" ) then
M <= X(6 downto 0) & "0000000000000" ;
N <= "00111" ;
elsif( X(19 downto 8) = "000000000000" ) then
M <= X(7 downto 0) & "000000000000" ;
N <= "01000" ;
elsif( X(19 downto 9) = "00000000000" ) then
M <= X(8 downto 0) & "00000000000" ;
N <= "01001" ;
elsif( X(19 downto 10) = "0000000000" ) then
M <= X(9 downto 0) & "0000000000" ;
N <= "01010" ;
elsif( X(19 downto 11) = "000000000" ) then
M <= X(10 downto 0) & "000000000" ;
N <= "01011" ;
elsif( X(19 downto 12) = "00000000" ) then
M <= X(11 downto 0) & "00000000" ;
N <= "01100" ;
elsif( X(19 downto 13) = "0000000" ) then
M <= X(12 downto 0) & "0000000" ;
N <= "01101" ;
elsif( X(19 downto 14) = "000000" ) then
M <= X(13 downto 0) & "000000" ;
N <= "01110" ;
elsif( X(19 downto 15) = "00000" ) then
M <= X(14 downto 0) & "00000" ;
N <= "01111" ;
elsif( X(19 downto 16) = "0000" ) then
M <= X(15 downto 0) & "0000" ;
N <= "10000" ;
elsif( X(19 downto 17) = "000" ) then
M <= X(16 downto 0) & "000" ;
N <= "10001" ;
elsif( X(19 downto 18) = "00" ) then
M <= X(17 downto 0) & "00" ;
N <= "10010" ;
elsif( X(19) = '0' ) then
M <= X(18 downto 0) & '0' ;
N <= "10011" ;
else
M <= X ;
N <= "10100" ;
end if ;
end if ;
end process ;
-----------------------------------------------------------
-- logalizm calculate --
-----------------------------------------------------------
LOG_CONV : process( M )
variable TMP : std_logic_vector(19 downto 0); -- 1-m
variable H : std_logic_vector(15 downto 0); -- 1-m
variable B1 : std_logic_vector(15 downto 0); -- H
variable B2 : std_logic_vector(31 downto 0); -- H^2
variable B3 : std_logic_vector(31 downto 0); -- H^3
variable B4 : std_logic_vector(31 downto 0); -- H^4
variable B5 : std_logic_vector(31 downto 0); --
variable B6 : std_logic_vector(31 downto 0); --
variable B7 : std_logic_vector(31 downto 0); --
variable B8 : std_logic_vector(31 downto 0); --
variable B9 : std_logic_vector(31 downto 0); --
variable B10 : std_logic_vector(31 downto 0); --
variable B11 : std_logic_vector(31 downto 0); --
variable B12 : std_logic_vector(31 downto 0); --
variable B13 : std_logic_vector(31 downto 0); --
variable C1 : std_logic_vector(15 downto 0); -- H
variable C2 : std_logic_vector(15 downto 0); -- H^2
variable C3 : std_logic_vector(15 downto 0); -- H^3
variable C4 : std_logic_vector(15 downto 0); -- H^4
variable C5 : std_logic_vector(15 downto 0); --
variable C6 : std_logic_vector(15 downto 0); --
variable C7 : std_logic_vector(15 downto 0); --
variable C8 : std_logic_vector(15 downto 0); --
variable C9 : std_logic_vector(15 downto 0); --
variable C10 : std_logic_vector(15 downto 0); --
variable C11 : std_logic_vector(15 downto 0); --
variable C12 : std_logic_vector(15 downto 0); --
variable C13 : std_logic_vector(15 downto 0); --
variable D : std_logic_vector(15 downto 0); --
begin
if( M = "00000000000000000000" ) then
Y <= (others=>'0') ;
else
-- TMP = -M
TMP := "00000000000000000000" - M ;
H := TMP(19 downto 4) ;
-- BEKI
B1 := H ;
B2 := H*H ;
B3 := B2(31 downto 16)*H ;
B4 := B2(31 downto 16)*B2(31 downto 16) ;
B5 := B4(31 downto 16)*H ;
B6 := B4(31 downto 16)*B2(31 downto 16) ;
B7 := B4(31 downto 16)*B3(31 downto 16) ;
B8 := B4(31 downto 16)*B4(31 downto 16) ;
B9 := B8(31 downto 16)*H ;
B10 := B8(31 downto 16)*B2(31 downto 16) ;
B11 := B8(31 downto 16)*B3(31 downto 16) ;
B12 := B8(31 downto 16)*B4(31 downto 16) ;
B13 := B8(31 downto 16)*B5(31 downto 16) ;
-- KEISU
C1 := B1 ;
C2 := '0' & B2(31 downto 17) ;
B3 := B3(31 downto 16)*CONS3 ;
C3 := B3(31 downto 16) ;
C4 := "00" & B4(31 downto 18) ;
B5 := B5(31 downto 16)*CONS5 ;
C5 := B5(31 downto 16) ;
B6 := B6(31 downto 16)*CONS3 ;
C6 := '0' & B6(31 downto 17) ;
B7 := B7(31 downto 16)*CONS7 ;
C7 := B7(31 downto 16) ;
C8 := "000" & B8(31 downto 19) ;
B9 := B9(31 downto 16)*CONS9 ;
C9 := B9(31 downto 16) ;
B10 := B10(31 downto 16)*CONS5 ;
C10 := '0' & B10(31 downto 17) ;
B11 := B11(31 downto 16)*CONS11 ;
C11 := B11(31 downto 16) ;
B12 := B12(31 downto 16)*CONS3 ;
C12 := "00" & B12(31 downto 18) ;
B13 := B13(31 downto 16)*CONS13 ;
C13 := B13(31 downto 16) ;
-- KASAN
D := C1+C2+C3+C4+C5+C6+C7+C8+C9+C10+C11+C12+C13 ;
-- KEKKA
Y <= D ;
end if ;
end process ;
-----------------------------------------------------------
-- output calculate --
-----------------------------------------------------------
--Feb.14.2005 TAK
OUTPUT_CALC : process( M,G) -- N, Y )
begin
if( M = "00000000000000000000" ) then
Z <= (others=>'0') ;
else
-- F <= N * LOG2V ;
-- G <= F - ("00000" & Y) ;
Z <= G(19 downto 0) ;
end if ;
end process ;
F <= N * LOG2V ;
G <= F - ("00000" & Y) ;
end RTL ;
------------------------------------------------------------------------
-- End of File --
------------------------------------------------------------------------
|
//-------------------------------------------------------------------
//
// This file is automatically generated by VHDL to Verilog Translator.
// Ver.1.08 Build Mar.6.2004
// www.sugawara-systems.com
// tech-support@sugawara-systems.com
// See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------
//----------------------------------------------------------------------
// Title Logalizm X (log(X)) --
// File LOG.vhd --
// Entity LOG --
// rev date coded contents --
// 001 98/11/17 ueno Make Original --
//----------------------------------------------------------------------
`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)
module log ( x, z );
input [19:0] x ;
output [19:0] z ;
reg [19:0] log_conv__tmp;
reg [15:0] log_conv__h;
reg [15:0] log_conv__b1;
reg [31:0] log_conv__b2;
reg [31:0] log_conv__b3;
reg [31:0] log_conv__b4;
reg [31:0] log_conv__b5;
reg [31:0] log_conv__b6;
reg [31:0] log_conv__b7;
reg [31:0] log_conv__b8;
reg [31:0] log_conv__b9;
reg [31:0] log_conv__b10;
reg [31:0] log_conv__b11;
reg [31:0] log_conv__b12;
reg [31:0] log_conv__b13;
reg [15:0] log_conv__c1;
reg [15:0] log_conv__c2;
reg [15:0] log_conv__c3;
reg [15:0] log_conv__c4;
reg [15:0] log_conv__c5;
reg [15:0] log_conv__c6;
reg [15:0] log_conv__c7;
reg [15:0] log_conv__c8;
reg [15:0] log_conv__c9;
reg [15:0] log_conv__c10;
reg [15:0] log_conv__c11;
reg [15:0] log_conv__c12;
reg [15:0] log_conv__c13;
reg [15:0] log_conv__d;
parameter [15:0] log2v=16'b1011000101110010;
parameter [15:0] cons3=16'b0101010101010101;
parameter [15:0] cons5=16'b0011001100110011;
parameter [15:0] cons7=16'b0010010010010010;
parameter [15:0] cons9=16'b0001110001110001;
parameter [15:0] cons11=16'b0001011101000101;
parameter [15:0] cons13=16'b0001001110110001;
parameter [15:0] cons15=16'b0001000100010001;
reg [15:0] y;
wire [20:0] f;
wire [20:0] g;
reg [19:0] m;
reg [4:0] n;
reg [19:0] z;
always @ (x ) begin
if ((x[19:0] === 20'b00000000000000000000))
begin
m <= {(19-0+1- 0){1'b0}};
n <= {(4-0+1- 0){1'b0}};
end
else
begin
if ((x[19:1] === 19'b0000000000000000000))
begin
m <= {x[0],19'b0000000000000000000};
n <= 5'b00001;
end
else if ((x[19:2] === 18'b000000000000000000))
begin
m <= {x[1:0],18'b000000000000000000};
n <= 5'b00010;
end
else if ((x[19:3] === 17'b00000000000000000))
begin
m <= {x[2:0],17'b00000000000000000};
n <= 5'b00011;
end
else if ((x[19:4] === 16'b0000000000000000))
begin
m <= {x[3:0],16'b0000000000000000};
n <= 5'b00100;
end
else if ((x[19:5] === 15'b000000000000000))
begin
m <= {x[4:0],15'b000000000000000};
n <= 5'b00101;
end
else if ((x[19:6] === 14'b00000000000000))
begin
m <= {x[5:0],14'b00000000000000};
n <= 5'b00110;
end
else if ((x[19:7] === 13'b0000000000000))
begin
m <= {x[6:0],13'b0000000000000};
n <= 5'b00111;
end
else if ((x[19:8] === 12'b000000000000))
begin
m <= {x[7:0],12'b000000000000};
n <= 5'b01000;
end
else if ((x[19:9] === 11'b00000000000))
begin
m <= {x[8:0],11'b00000000000};
n <= 5'b01001;
end
else if ((x[19:10] === 10'b0000000000))
begin
m <= {x[9:0],10'b0000000000};
n <= 5'b01010;
end
else if ((x[19:11] === 9'b000000000))
begin
m <= {x[10:0],9'b000000000};
n <= 5'b01011;
end
else if ((x[19:12] === 8'b00000000))
begin
m <= {x[11:0],8'b00000000};
n <= 5'b01100;
end
else if ((x[19:13] === 7'b0000000))
begin
m <= {x[12:0],7'b0000000};
n <= 5'b01101;
end
else if ((x[19:14] === 6'b000000))
begin
m <= {x[13:0],6'b000000};
n <= 5'b01110;
end
else if ((x[19:15] === 5'b00000))
begin
m <= {x[14:0],5'b00000};
n <= 5'b01111;
end
else if ((x[19:16] === 4'b0000))
begin
m <= {x[15:0],4'b0000};
n <= 5'b10000;
end
else if ((x[19:17] === 3'b000))
begin
m <= {x[16:0],3'b000};
n <= 5'b10001;
end
else if ((x[19:18] === 2'b00))
begin
m <= {x[17:0],2'b00};
n <= 5'b10010;
end
else if ((x[19] === 1'b0))
begin
m <= {x[18:0],1'b0};
n <= 5'b10011;
end
else
begin
m <= x;
n <= 5'b10100;
end
end
end //always
always @ (m ) begin
if ((m === 20'b00000000000000000000))
y <= {(15-0+1- 0){1'b0}};
else
begin
log_conv__tmp = (20'b00000000000000000000 - m);
log_conv__h = log_conv__tmp[19:4];
log_conv__b1 = log_conv__h;
log_conv__b2 = (log_conv__h * log_conv__h);
log_conv__b3 = (log_conv__b2[31:16] * log_conv__h);
log_conv__b4 = (log_conv__b2[31:16] * log_conv__b2[31:16]);
log_conv__b5 = (log_conv__b4[31:16] * log_conv__h);
log_conv__b6 = (log_conv__b4[31:16] * log_conv__b2[31:16]);
log_conv__b7 = (log_conv__b4[31:16] * log_conv__b3[31:16]);
log_conv__b8 = (log_conv__b4[31:16] * log_conv__b4[31:16]);
log_conv__b9 = (log_conv__b8[31:16] * log_conv__h);
log_conv__b10 = (log_conv__b8[31:16] * log_conv__b2[31:16]);
log_conv__b11 = (log_conv__b8[31:16] * log_conv__b3[31:16]);
log_conv__b12 = (log_conv__b8[31:16] * log_conv__b4[31:16]);
log_conv__b13 = (log_conv__b8[31:16] * log_conv__b5[31:16]);
log_conv__c1 = log_conv__b1;
log_conv__c2 = {1'b0,log_conv__b2[31:17]};
log_conv__b3 = (log_conv__b3[31:16] * cons3);
log_conv__c3 = log_conv__b3[31:16];
log_conv__c4 = {2'b00,log_conv__b4[31:18]};
log_conv__b5 = (log_conv__b5[31:16] * cons5);
log_conv__c5 = log_conv__b5[31:16];
log_conv__b6 = (log_conv__b6[31:16] * cons3);
log_conv__c6 = {1'b0,log_conv__b6[31:17]};
log_conv__b7 = (log_conv__b7[31:16] * cons7);
log_conv__c7 = log_conv__b7[31:16];
log_conv__c8 = {3'b000,log_conv__b8[31:19]};
log_conv__b9 = (log_conv__b9[31:16] * cons9);
log_conv__c9 = log_conv__b9[31:16];
log_conv__b10 = (log_conv__b10[31:16] * cons5);
log_conv__c10 = {1'b0,log_conv__b10[31:17]};
log_conv__b11 = (log_conv__b11[31:16] * cons11);
log_conv__c11 = log_conv__b11[31:16];
log_conv__b12 = (log_conv__b12[31:16] * cons3);
log_conv__c12 = {2'b00,log_conv__b12[31:18]};
log_conv__b13 = (log_conv__b13[31:16] * cons13);
log_conv__c13 = log_conv__b13[31:16];
log_conv__d = ((((((((((((log_conv__c1 + log_conv__c2) + log_conv__c3) + log_conv__c4) + log_conv__c5) + log_conv__c6) + log_conv__c7) + log_conv__c8) + log_conv__c9) + log_conv__c10) + log_conv__c11) + log_conv__c12) + log_conv__c13);
y <= log_conv__d;
end
end //always
always @ (m or g ) begin
if ((m === 20'b00000000000000000000))
z <= {(19-0+1- 0){1'b0}};
else
z <= g[19:0];
end //always
assign {f}=(n * log2v);
assign {g}=(f - {5'b00000,y});
endmodule
|
//Feb.13.2005
//Feb.15.2005
//Tak.Sugawara
module cordic_bench_test;
parameter cos_sin_mode=1'b0,atan_mode=1'b1;
parameter integer bit_precision=10;//11 fails
parameter integer atan_precision=11;//12 fails
parameter integer precision=bit_precision;//
parameter real allowable_error=1.0/(2**precision);
parameter real allowable_error_atan=1.0/(2**atan_precision);
parameter integer scale_power=14;//bit
parameter integer scale=2**scale_power;//16384
parameter real max_test_angle_degree=91;//max of 100 degree
reg [15:0] in_x=0 ;
reg [15:0] in_y=0 ;
reg signed [15:0] in_angle=0 ;
reg in_start=0;
reg in_mode=cos_sin_mode;
reg clk=0;
reg enable=0;
reg xrst=0;
wire out_finish;
wire signed [15:0] out_x ;
wire signed [15:0] out_y ;
wire signed [15:0] out_z ;
//
real in_angle_r;
real max_in_angle_r;//
real hard_sin,hard_cos;//
real max_angle_r;
real h_sin_limit,l_sin_limit;
real h_cos_limit,l_cos_limit;
integer i;
real work,work1;
real x_r,y_r,hard_z,angle_z;
always #10 clk=~clk;
cordic dut ( in_x, in_y, in_angle, in_start, in_mode, clk, enable, xrst, out_finish, out_x, out_y, out_z );
initial begin
//sin/cos test
//test 0->90degree
repeat(2) @(posedge clk);
@(negedge clk);
xrst=1;
in_start=1;
enable=1;
begin :for_loop1
for (i=0; 1;i=i+1) begin
in_angle=i;
@(negedge clk) in_start=0;
repeat(3) @(negedge clk);
wait (out_finish);//wait hardware calculation
in_angle_r=$itor(in_angle)/$itor(scale);
hard_sin=$itor(out_y)/$itor(scale);
hard_cos=$itor(out_x)/$itor(scale);
work=$sin(in_angle_r);
work1=allowable_error;
h_sin_limit=$sin(in_angle_r)+allowable_error;//evaluate as output-bit-precision
l_sin_limit=$sin(in_angle_r)-allowable_error;
h_cos_limit=$cos(in_angle_r)+allowable_error;
l_cos_limit=$cos(in_angle_r)-allowable_error;
if (h_sin_limit < hard_sin)begin
$display("sin max error detected %g %g",h_sin_limit,hard_sin);
$stop;
end
if (l_sin_limit > hard_sin) begin
$display("sin min error detected %g %g",l_sin_limit,hard_sin);
end
if (h_cos_limit < hard_cos)begin
$display("cos max error detected %g %g",h_cos_limit,hard_sin);
$stop;
end
if (l_cos_limit > hard_cos) begin
$display("cos min error detected %g %g",l_cos_limit,hard_sin);
end
if (i%1000==0)
$display("i=%d in_angle_r=%g sin=%g hadware_result=%g",i,in_angle_r,$sin(in_angle_r),hard_sin);
max_angle_r=max_test_angle_degree/180.*$M_PI;
if (max_angle_r < in_angle_r) disable for_loop1;//exit test loop
@(negedge clk) in_start=1;
end
end //for loop
//test 0->-90degree
@(negedge clk);
in_start=1;
enable=1;
begin :for_loop2
for (i=0; 1;i=i+1) begin
in_angle=-i;
@(negedge clk) in_start=0;
repeat(3) @(negedge clk);
wait (out_finish);//wait hardware calculation
in_angle_r=$itor(in_angle)/$itor(scale);
hard_sin=$itor(out_y)/$itor(scale);
hard_cos=$itor(out_x)/$itor(scale);
work=$sin(in_angle_r);
work1=allowable_error;
h_sin_limit=$sin(in_angle_r)+allowable_error;//evaluate as output-bit-precision
l_sin_limit=$sin(in_angle_r)-allowable_error;
h_cos_limit=$cos(in_angle_r)+allowable_error;
l_cos_limit=$cos(in_angle_r)-allowable_error;
if (h_sin_limit < hard_sin)begin
$display("sin max error detected %g %g",h_sin_limit,hard_sin);
$stop;
end
if (l_sin_limit > hard_sin) begin
$display("sin min error detected %g %g",l_sin_limit,hard_sin);
end
if (h_cos_limit < hard_cos)begin
$display("cos max error detected %g %g",h_cos_limit,hard_sin);
$stop;
end
if (l_cos_limit > hard_cos) begin
$display("cos min error detected %g %g",l_cos_limit,hard_sin);
end
if (i%1000==0)
$display("i=%d in_angle_r=%g sin=%g hadware_result=%g",i,in_angle_r,$sin(in_angle_r),hard_sin);
max_angle_r=max_test_angle_degree/180.*$M_PI;
if (-max_angle_r > in_angle_r) disable for_loop2;//exit test loop
@(negedge clk) in_start=1;
end
end //for loop
$display("Cordic sin/cos test passed");
//atan (y/x)
//test scheme
// 1>=x>0 assuming x**2+y**2=1 y=sqrt(1-xx*2);
//
xrst=0;
repeat(2) @(negedge clk);
@(negedge clk);
in_start=1;
enable=1;
xrst=1;
in_mode=atan_mode;
for (i=0;i<= scale;i=i+1) begin
in_x=i;//Start, with given in_x and in_y
x_r=$itor(i)/scale;
work=1.0-x_r**2;
y_r=$sqrt(work);
work1=y_r*scale;
in_y=$rtoi(work1);
@(negedge clk) in_start=0;//deassert _instart
repeat(3) @(negedge clk);
wait (out_finish);//wait hardware calculation
@(negedge clk);
hard_z=$itor(out_z)/scale;//get hardware result.
if (i==0) angle_z=$M_PI/2.0;
else if (i==scale) angle_z=0.0;
else angle_z=$atan(y_r/x_r);
if (hard_z > angle_z+allowable_error_atan) begin
$display("Error Detected atan max");
$stop;//assert(0);
end
if (hard_z < angle_z-allowable_error_atan) begin
$display("Error Detected atan min");
$stop;//assert(0);
end
@(negedge clk) in_start=1;
end
$display("atan(y/x) test passed");
$finish;
end
endmodule
|
| i= 0 in_angle_r=0 sin=0 hadware_result=0.000244141 i= 1000 in_angle_r=0.0610352 sin=0.0609973 hadware_result=0.0609131 i= 2000 in_angle_r=0.12207 sin=0.121767 hadware_result=0.121948 i= 3000 in_angle_r=0.183105 sin=0.182084 hadware_result=0.18219 i= 4000 in_angle_r=0.244141 sin=0.241723 hadware_result=0.241943 i= 5000 in_angle_r=0.305176 sin=0.300461 hadware_result=0.300415 i= 6000 in_angle_r=0.366211 sin=0.35808 hadware_result=0.357971 i= 7000 in_angle_r=0.427246 sin=0.414366 hadware_result=0.414246 i= 8000 in_angle_r=0.488281 sin=0.469109 hadware_result=0.469177 i= 9000 in_angle_r=0.549316 sin=0.522104 hadware_result=0.521973 i= 10000 in_angle_r=0.610352 sin=0.573156 hadware_result=0.573181 i= 11000 in_angle_r=0.671387 sin=0.622072 hadware_result=0.622009 i= 12000 in_angle_r=0.732422 sin=0.668672 hadware_result=0.668701 i= 13000 in_angle_r=0.793457 sin=0.712782 hadware_result=0.712769 i= 14000 in_angle_r=0.854492 sin=0.754238 hadware_result=0.754395 i= 15000 in_angle_r=0.915527 sin=0.792884 hadware_result=0.79303 i= 16000 in_angle_r=0.976563 sin=0.828578 hadware_result=0.828491 i= 17000 in_angle_r=1.0376 sin=0.861186 hadware_result=0.861328 i= 18000 in_angle_r=1.09863 sin=0.890586 hadware_result=0.890686 i= 19000 in_angle_r=1.15967 sin=0.91667 hadware_result=0.91687 i= 20000 in_angle_r=1.2207 sin=0.939341 hadware_result=0.93927 i= 21000 in_angle_r=1.28174 sin=0.958513 hadware_result=0.958435 i= 22000 in_angle_r=1.34277 sin=0.974115 hadware_result=0.974121 i= 23000 in_angle_r=1.40381 sin=0.98609 hadware_result=0.986145 i= 24000 in_angle_r=1.46484 sin=0.994392 hadware_result=0.994324 i= 25000 in_angle_r=1.52588 sin=0.998991 hadware_result=0.999023 i= 26000 in_angle_r=1.58691 sin=0.99987 hadware_result=0.999573 i= 0 in_angle_r=0 sin=0 hadware_result=0.000244141 i= 1000 in_angle_r=-0.0610352 sin=-0.0609973 hadware_result=-0.0606689 i= 2000 in_angle_r=-0.12207 sin=-0.121767 hadware_result=-0.121582 i= 3000 in_angle_r=-0.183105 sin=-0.182084 hadware_result=-0.181946 i= 4000 in_angle_r=-0.244141 sin=-0.241723 hadware_result=-0.241943 i= 5000 in_angle_r=-0.305176 sin=-0.300461 hadware_result=-0.300415 i= 6000 in_angle_r=-0.366211 sin=-0.35808 hadware_result=-0.358032 i= 7000 in_angle_r=-0.427246 sin=-0.414366 hadware_result=-0.414307 i= 8000 in_angle_r=-0.488281 sin=-0.469109 hadware_result=-0.468872 i= 9000 in_angle_r=-0.549316 sin=-0.522104 hadware_result=-0.52179 i= 10000 in_angle_r=-0.610352 sin=-0.573156 hadware_result=-0.573181 i= 11000 in_angle_r=-0.671387 sin=-0.622072 hadware_result=-0.622009 i= 12000 in_angle_r=-0.732422 sin=-0.668672 hadware_result=-0.668701 i= 13000 in_angle_r=-0.793457 sin=-0.712782 hadware_result=-0.712769 i= 14000 in_angle_r=-0.854492 sin=-0.754238 hadware_result=-0.754395 i= 15000 in_angle_r=-0.915527 sin=-0.792884 hadware_result=-0.792908 i= 16000 in_angle_r=-0.976563 sin=-0.828578 hadware_result=-0.828369 i= 17000 in_angle_r=-1.0376 sin=-0.861186 hadware_result=-0.861206 i= 18000 in_angle_r=-1.09863 sin=-0.890586 hadware_result=-0.890564 i= 19000 in_angle_r=-1.15967 sin=-0.91667 hadware_result=-0.91687 i= 20000 in_angle_r=-1.2207 sin=-0.939341 hadware_result=-0.93927 i= 21000 in_angle_r=-1.28174 sin=-0.958513 hadware_result=-0.958435 i= 22000 in_angle_r=-1.34277 sin=-0.974115 hadware_result=-0.974121 i= 23000 in_angle_r=-1.40381 sin=-0.98609 hadware_result=-0.986023 i= 24000 in_angle_r=-1.46484 sin=-0.994392 hadware_result=-0.994324 i= 25000 in_angle_r=-1.52588 sin=-0.998991 hadware_result=-0.999023 i= 26000 in_angle_r=-1.58691 sin=-0.99987 hadware_result=-0.999451 Cordic sin/cos test passed atan(y/x) test passed |
|---|
------------------------------------------------------------------------ -- Title CORDIC calculater sin(x), cos(x), atan(y/x) -- -- File CORDIC.vhd -- -- Entity CORDIC -- -- rev date coded contents -- -- 001 99/01/06 ueno Make Original -- ------------------------------------------------------------------------ library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all ; --use IEEE.std_logic_signed.all ; --use IEEE.std_logic_arith.all ; ------------------------------------------------------------------------ -- entity -- -------------------------------------------------------------------- |